Chamber electronics Status, Plans, Needs

1
Chamber electronics Status, Plans, Needs

• Sten Hansen and Wu, Jinyuan
• Fermilab, PPD/EED
• Dec. 2006

2
High-Speed Differential Interfaces Cyclone II
devices can transmit and receive data through
LVDS signals at a data rate of up to 640 Mbps and
805 Mbps, respectively. For the LVDS transmitter
and receiver, the Cyclone II devices input and
output pins support serialization and
deserialization through internal logic.
6000 Channels
7000 Channels
RJ 45 Connectors
RJ 45 Connectors
Power
Power
FPGA As TDC
FPGA As TDC
32 Channels of LVDS Receivers
32 Channels of LVDS Receivers
8 Chan Amp/Disc
8 Chan Amp/Disc
8 Chan Amp/Disc
8 Chan Amp/Disc
32 Channel Amp/Disc
3
8 Channel Amp/Disc One per 8 channel Card, Four
per 32 channel Card
Vth
Test Pls
LVDS Comparator
UPC 1663
Wire 0
-
-
RT
Hit 0


14 Balun
Vth 0
DacClk
DacSDat
Octal Serial DAC
Vth
Test Pls
LVDS Comparator
Vth 0
UPC 1663
Wire 7
-
-
RT
Hit 7


14 Balun
Test Pls Mag
Open Collector Driver
Test Pls Trig
Test Pls
LVDS TTL Adapter
4
TDC Card Arrangement
To Readout Card
Cat 5 Cable
Power Cable
Power 48V
RJ 45 Connectors
SDRam
DC-DC Converter
uC
FPGA
32 Channels of LVDS Receivers
5
907 TPC/TDC Readout Card Block Diagram
Ext RF
Dtack
Start Read
VME Ctrl
Front Panel LEMOs
V Ad
Trig
V Dat
Tst Pls
Serial Control Path
A
uC
VME Bus
D
FPGA
53MHz VXO
Clock
Ø Det
V Ad
A
A
Dual Port RAM
V Dat
D
D
To Front Ends
Event Data
Trig Data
6
Appearance of Readout Card
Shown here is Fermilab Beam Loss Monitor (BLM)
Control Card
RAM Buffers
VME Interface
RJ45 Connectors (8/card for real design)
FPGA
7
TDC-Readout System
TDC Cards
Readout Cards
8
TDC Using FPGA (LSB 1ns-)
2x Sampling 250 MHz 2ns(LSB), 577ps(RMS) 400
MHz 1.25ns(LSB), 361ps(RMS)
4x Sampling 250 MHz 1ns(LSB), 288ps(RMS) 400
MHz 625ps(LSB), 180ps(RMS)
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DDR TDC Test Stand
10
DDR TDC (1.2ns/bin)
11
FPGA TDC With LSB lt 0.5ns

• This scheme uses current FPGA technology ?
• Low cost chip family can be used. (e.g.
  EP1K10QC208-2 15.25) ?
• Fine TDC precision can be implemented in slow
  devices (e.g., 0.4 ns (120ps RMS) in a 200 MHz
  chip). ?

IN
This is a 2002 work. To be studied for 2006
devices.
CLK
12
Delay Chain Digital Compensation

• Use longer delay line.
• Some signals may be registered twice at two
  consecutive clock edges.

IN
N2-N1(1/f)/Dt

• The two measurements can be used
• to calibrate the delay.
• to reduce digitization errors.

CLK
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Some Words About FPGA TDC

• Many TDC jobs can be done with FPGA purely based
  on digital process.
• FPGA TDC can be built near the amplifier
  discriminator. Timing signals need not to travel
  in long cable.
• Absolute time is digitized continuously. The
  timing resolution is factor of sqrt(2) better
  than in start-stop scheme.
• Higher precision (LSBlt0.5ns) TDC is possible.

14
Clock, Reset and L1 Trigger
Which cycle is the 0th one?
The FPGA detects this marker to reset the coarse
time counter.
0
1
2
N
N1
N2
N-1
Must send clock. But Reset? L1?
This marker indicates L1 trigger at clock cycle N.
15
C5 Clock-Command Combined Carrier Coding
Message can be sent along with clock
Message carried in clock signal doesnt destroy
PLL stability
16
TDC, Pipeline, Zero-Suppression etc.
Hit times are buffered in pipeline waiting for L1
trigger.
Chamber hits are digitized continuously.
Chamber hits may or may not participate L1
trigger.
Zero-suppression are done after (not before) the
pipeline when L1 comes.
Event data are buffered in the FIFO (possibly in
SDRAM) to be readout.
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Summary

• TDC near front-end using FPGA is chosen as basic
  scheme.
• Appearances of front-end, TDC and readout cards
  are conceptually known.
• Clock, reset and L1 distribution,
  zero-suppression scheme and other details are to
  be determined. But there are sets of standard
  approaches to choose from.

18
Beyond

• The TDC-readout system has excessive
  capabilities. Dont hastate to ask more if you
  need.
• TDC Arrival time pulse width.
• Chamber info in trigger.