Status of the electronics systems of the MEG experiment

1
Status of the electronics systems of the MEG
experiment
2
Electronic chain
3
DAQ and control
Ancillary system
3 crates
6 crates
4
HV
5
HV System

• 4 different requirements
• Lxe 1000V , 100 uA
• TC bars 2400V, 1 mA
• TC curved 500V, lt1 uA
• DC 2400V, 1 uA

• System works from 10V 2400V, 1.5mA, 1uA
  resolution, special version for 1nA resolution
• Current-trip feature implemented and tested, the
  HV-off time determined by de-charging capacitance
• HV will end at backplane
• Users have to decide about connectors
• 4-channel system in 3HE crate
• (40 channels are currently in use at PSI)
• 10-channel system in 6HE crate
• 400 channels in preparation, ready by September

http//www.fischerconnectors.com/
1-15 kV
6
HV crate

• 10 chn per board
• 180 chn per 3 HE crate
• Back side connector

HV passes through backplane
7
Splitters
8
Splitter project requirements

• Inputs
• 828 Lxe 120 TC channels
• Single ended (Rin50O)
• Dual row headers connectors
• Test
• High-precision and constant amplitude levels
• Outputs
• DRS
• Full bandwidth
• Gain 1
• Trigger
• 100 MHz bandwidth
• Gain 1
• Analog Adder
• 4-channels sum
• 100 MHz bandwidth
• Gain 1
• Differential (Rout120O)
• Standard profile boxed header connectors (3M

9
Components selected

• THS4509 1.9GHz, 6600 V/µs Low Distortion fully
  Differential Amplifier
• DRS outputs driver
• AD8137 Low Distortion Differential ADC Driver
• Trigger and sum output driver.

10
Prototype

• In the first half of 2005 the technical
  requirements for splitter were defined
• The final prototype design started immediately
• The 2-channels prototype was completed in March
  2005 and tested

11
Crosstalk test

• Input pulse
• 1.6V amplitude (Vout0.8V, Vout--0.8V)
• lt1 ns risetime
• Input crosstalk (Metallic enclosure)
• Crosstalk Ch1?Ch4 lt0.1
• Crosstalk Ch2?Ch4 0.5
• Crosstalk Ch3?Ch4 1.5
• Inside the board output connector crosstalks
  (input connector contribution excluded)
• Crosstalk Ch3?Ch4 1.5
• Inside the board crosstalk
• Crosstalk Ch3?Ch4 0.5

12
Final splitter board
Full BW Output (34-pins)
Input (64-pins)
Sum output (16-pins)
Reduced BW Output (34-pins)
Power and test
13
Test circuit

• The calibration of the DRS channels needs
  constant levels voltage on all inputs
• A step voltage generator, with 4 voltage levels,
  was developed
• Levels are defined with high precision low noise
  reference IC (LM4140) with
• 0.1 accuracy and
• low temperature coefficient (3ppm/C)
• This circuit will be implemented on the backplane
  and it will feed all the splitter cards contained
  in the crate.

14
Production

• October 05 test of the final prototype
• December 05 end of full production
• October 05 order of the cables
• March 05 installation

15
TC
16
PMT ramp generator
B
to Splitter
Analog signals to DRS and trigger
PMT
B
S
TC Analog Sign. Monitor
Passive Splitter
RAMP GEN.
D/D
6U Eurocards boards 8 boards
to Splitters
Signals to DRS
Dual Threshold Discriminator
NIM Signal for any possible use
17
APD pre-amplifier

• Input 10 APD
• Ouput
• 10 shaped and discriminated channels for the hit
  register
• 1 analog sum for the trigger
• ENC 1500 e rms
• Risetime5 ns
• Pulse-length 50 ns

18
Hit encoder/register
6U VME boards 5 boards
152
Curved TC right side
152
Curved TC left side
AB
Mask Right
Mask Left
152
Clock control signal
Encoder
Control Logic
Trigger and monitor
VME bus
Register
FPGA
19
Production

• PMT ramp generator
• October 05 design of the final board
• January 06 system delivery (8 boards - 6U
  Eurocards)
• APD pre amplifiers
• September 05 design of the final APD
  pre-amplifiers
• October 05 test of the final prototype
• December 05 system delivery (80 cards)
• APD hit registers
• December 05 board design
• April 06 system delivery (6 boards 6U VME)

20
DC
21
DC electronics
At interface He bag outside Cobra
inverting
anode
OR small R
Preamplifier 16 x (2 x 9) x 6 1728 channels
16 ch. cable to DRS
cathode
OR Large R
Non inverting
22
Production

• DC electronics
• September 05 design of the final pre-amplifiers
  
• November 05 test of the final prototype
• January 06 system delivery

23
Trigger
24
Trigger system structure
2 boards
2 VME 6U 1 VME 9U Located on the platform
LXe inner face (216 PMTs)
2 x 48
92 boards
. . .
1 board
LXe lateral faces back (216 PMTs) 4 in 1 lat.
(144x2 PMTs) 4 in 1 up/down (54x2 PMTs) 4 in 1
9 x 48
2 x 48
1 board
2 x 48
Timing counters curved (640 APDs) 8 in 1 u/d
stream (30x2 PMTs)
1 board
2 boards
Drift chambers 1616 channels
2 x 48
25
Type1 Present Status

• CPLD Coolrunner II (XC2C284-10-FG324) ?
• Type1 CPLD design completed and simulated ?
• FPGA VIRTEX II- PRO (XC2VP20-7-FF1152) ?
• Type1-1 LXe front face (Frequency 116 MHz) ?
• Type1-2 LXe lateral faces in progress
• Type1-3 TC x
• Type1-4 DC x
• PCB
• import FPGA ?
• Board Schematics ?
• Footprints and routing ?
• Gerber files ?
• PCB production in progress ?
• Board mounting x

26
Type1
27
Type2 Present Status

• CPLD Coolrunner II (XC2C284-10-FG324) ?
• Type1 CPLD design completed and simulated ?
• FPGA VIRTEX II- PRO (XC2VP40-7-FF1152) ?
• Type2-0 Final Level completed ? ?
• Type2-1 LXe inner faces x
• Type2-2 LXe lateral faces x
• Type2-3 TC x
• PCB
• import FPGA ?
• Board Schematics ?
• Footprints and routing ?
• Gerber files ?
• PCB production in progress ?
• Board mounting x

28
Type2
29
Ancillary boards
Event counter Trigger pattern
to DRS
Busy
from DAQ
START STOP
START STOP SYNC RES CLK
ANCILLARY Mother
. . .
CLK 20 MHz
SYNC RES
VME
ANCILLARY Daughters
60 x CLK
to DRS
30
Ancillary Present Status

• CPLD Coolrunner II (XC2C284-10-FG324) ?
• Type1 CPLD design completed and simulated ?
• Components MAX9153 3D3418 ?
• PCB
• import FPGA ?
• Board Schematics ?
• Footprints and routing in progress ?
• Gerber files x
• PCB production x
• Board mounting x

31
Trigger components
All components already delivered, including LVDS
interconnect cables
32
Trigger test

• The test of the final boards can be done in
  September, as foreseen in the schedule
• The test will be done by using Struck interfaces.
  The present read-out speed of all trigger WFS for
  the full system is around 15 Hz.
• This rate is more than adequate for the trigger
  system needs calibration, efficiency
  measurements and stability
• We are investigating the possibility of
  increasing the readout speed.

33
Trigger schedule
2002
2003
2004
2005
Prototype Board
Final Prototype
Full System
partial installation
Prototype Board
Final Prototype
Full system
1st lot of components ordered
full install.
2nd lot of components
Test
Milestone
Assembly
Design
Manufactoring
34
Domino chip status
35
DRS2 plastic PLCC

• 674 additional chips produced
• 150 chips for MAGIC
• 4200 channels for DC/TC/LXe

36
Improved Sampling Range
Domino wave can be operated below 500 MHz if
started with a longer starting pulse. Minimum is
5 MHz. Modified start pulse makes operation at
500 MHz stable.
37
Spikes in last beam time
38
Cause of spikes
At 33 MHz, spike is always sampled, independent
of FADC phase
At 16.5 MHz, FADC phase can be adjusted to skip
spike
39
Fixing spikes
before
Spikes were fixed by reducing readout speed from
33 MHz to 16.5 MHz. Longer dead time will be
compensated by having two FADCs in new mezzanine
board
after
40
Double Peaks
Double peaks in signals were caused by crosstalk
from domino tap signal used for domino frequency
measurement
Domino Tap signal
crosstalk
Fix different routing, multilayer, ground shield
Clock signal
41
CMC connection
42
Timing Stability
Frequency Stabilization
Trigger Signal Sampling
domino wave
FADC
8 inputs
FPGA
Freq. Cntr
16-bit DAC
shift register
Implemented in FPGA (VHDL) ? 400 ps stability
Low-jitter clock
MUX
43
Recovery of Timing
4) Timing of all PMT pulses is expressed relative
to t0 point
1) Trigger publishes phase f of trigger signal f
relative to clock in multiples of 10 ns
f
50 ns
2) Each DAQ card determines and fits
Time-Zero-Edge in clock signal and uses this as
t0
3) Measure pulse width of clock to derive domino
speed
Domino speed stability of 10-3 400ps
uncertainty for full window 25ps uncertainty
for timing relative to edge
44
Domino wave jitter
30 ns

• 33 MHz calibration clock
• Peak fit with reference pulse
• Average over all pulses for many events
• Jitter is 115 ps
• Maximum distance of any signal to next clock peak
  is 15 ns ? accuracy should be 60 ps

45
Calibration

• Measure Vin Vout characteristics with precise
  DC power supply at the DRS2 input for all bins
• Fit characteristics and use it for calibration
• One curve needed per bin, under improvement
• Is now done offline, will later be done online
  (front-end or FPGA)

mV
ADC counts / 10
46
Effect of calibration

• Calibration in mV
• Fixed pattern noise is gone
• Crosstalk from clock remains

47
Noise Measurement
Trigger
mV
0.55 mV / 1V gt 11 bits
mV
48
Crosstalk inside DRS
Rise time 0 ? 1 0 ? 2 0 ? 7
2 ns 2.8 1.6 1.3
8 ns 1.1 0.6 0.8

• Measured with signal generator
• Current crosstalk is not good but acceptable for
  the moment
• Since integral of crosstalk is zero, it should
  mainly affect the timing and pile-up recognition
• Expect crosstalk in DRS3 (differential inputs)
  smaller by 5x

49
Current readout mode

• First implemented in DRS2
• Sampled charge does not leave chip
• Current readout less sensitive to cross-talk etc.

R
I
Vin
Vout
read
write
. . .
C
I c1 Vin c2 Vin kT
50
Temperature Dependence
Tc 1.4 / ºC
Vout V
T º C
DRS2 has a marked dependence on the temperature
51
Strategy for Temperature Problem

• Put temperature sensors on boards
• Keep electronics temperature stable (control air
  condition with temperature sensors on electronics
  to compensate for day-night cycles)
• Calibrate temperature drifts as much as possible,
  expect 1 accuracy by using the constant level
  test pulses
• Design DRS3 with temperature compensation

Vin
Vout
write
C
Ib
Matched Transistors
52
DRS board production

• New mezzanine card by end of July ? 192 channels
• Test of mezzanine card in September
• Next mezzanine card production cycle in October ?
  O(1000) channels
• All channels (2000 DC, 800 XE, 200 TC) before
  detectors become ready
• Start design of DRS3 in October
• Replace DRS2 by DRS3 in the second half of 2006

53
DRS3 Design

• New DRS3 design
• All channels differential
• Additional shielding between channels (ground
  bond wires)
• Reduced readout time (5x) minimized dead time
• Internal cascading allows for n x 1024 sampling
  bins
• Intrinsic temperature compensation

54
DRS (DAQ)
2003
2004
2005
2006
DRS2
DRS2 production 1600 chn
DRS2 test board
DRS3
VME boards
Full System
DRS2
DRS2 production 4000 chn
DRS2 test board
4000 chn
DRS3
VME boards
Full System
Replacement
Milestone
Test
Assembly
Design
Manufactoring
55
Conclusions

• An electronics integration scheme has been
  developed
• Minor details needs to be fixed
• All key electronics elements will be available
  before March 06
• A test of the final electronics systems, together
  with crates, in magnetic field environment is
  planned in autumn

56
Electronic/DAQ overview
area
Trigger
21 VME crates
216
PMT
trigger
LXe
ready
612
6 VME crates
PMT
optical fiber (20m)
DRS Board (32chn) CPU
Front-End PCs
60
Rack PC (Linux)
TC
PMT
Ramp
Rack PC (Linux)
SIS 3100
SIS 3100
Rack PC (Linux)
1920
Rack PC (Linux)
DRS Board (32chn) CPU
DC
DC
Pre-Amp
Rack PC (Linux)
Rack PC (Linux)
Gigabit Ethernet
Rack PC (Linux)
Rack PC (Linux)
Raw data 2920 channels Up to 100 Hz 50 / 10 /
10 occupancy 2kB / waveform -gt 5 x 25 MB/sec.
Rack PC (Linux)
Fitted data 10 Hz waveform data -gt 1.2
MB/sec 90 Hz ADC / TDC data -gt 0.9 MB/sec
Rack PC (Linux)
On-line farm
storage