Status of the electronics systems of the MEG experiment

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Status of the electronics systems of the MEG
experiment
2
HV system

• External HV power supply
• Control and regulation through MSCB
• 10 chn per board
• 180 chn per 3 HE crate
• Back side connector

• 4 different requirements
• Lxe 1000V , 100 uA
• TC bars 2400V, 1 mA
• TC curved 500V, lt1 uA
• DC 2400V, 1 uA
• 50 channels successfully tested on the LP for a
  couple of months
• 1000 channels for LXe, TC and DC in production
• Ready by June 06

3
Splitter boards

• Studies on the cross-talk on twisted cables
  suggested better insulation among the
  full-bandwidth output for DRS
• High bandwidth output layout was changed for new
  connector from JAE
• Cross-talk expected lt 1

trigger/DRS
Input
DRS
trigger
Power
4
Splitter backplane layout

• The DRS calibration circuit has been included on
  the backplane
• It provides programmable DC levels on all the
  splitter outputs (0.-2. V at 1mV resolution)
• Control through MSCB
• A special calibration signal is provided by the
  trigger system

Example of a calibration pattern
5
Splitter orders status

• Parts all ordered, many arrived
• Cables
• Input cables carriers partially delivered
• Output 34p tw 2.54 pitch cables connectors
  (trigger) delivered
• Output 10p tw 2.54 pitch cables connectors
  (sum) delivered
• Output 68p tw 1.27 pitch cables connectors
  (DRS) ordered
• Crates
• 9U Crates with accessories ordered
• Fans delivered
• Power supply ordered
• Backplane printed circuit ordered
• Backplane connectors delivered
• Cards
• Printed circuit ordered
• Card components ordered
• Front panels ordered
• Mechanical accessories delivered

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TC discriminator cards

• Timing measurement
• Eurocard 6U height
• 8 boards
• Hosted in the splitter crate

B
to Splitter
Analog signals to DRS and trigger
B
PMT
S
TC Analog Sign. Monitor
Passive Splitter
Prototype under test at Frascati Delivery in
May Installation in June
RAMP GEN.
D/D
to Splitters
Signals to DRS
Dual Threshold Discriminator
NIM Signal for any possible use
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TC fibers
TC mezzanine board
Output for the trigger system

• APD F.E. card
• Front-end prototype for APD under test
• Final prototypes construction will start by 15th
  of february
• Final production 3 weeks after acceptance.
• Delivery expected in May
• Same schedule for concentrator cards and
  mezzanine for VME-VPC board.
• FPGA CODE (V1.01) ready. Soon will start the
  evaluation process that will take 1 months

PSI GPVME board
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Trigger system structure
2 boards
LXe front face (216 PMTs)
2 x 48
552 boards
LXe lateral faces back (216 PMTs) 4 in 1 lat.
(144x2 PMTs) 4 in 1 up/down (54x2 PMTs) 4 in 1
. . .
1 board
9 x 48
2 x 48
1 board
Timing counters curved (640 APDs) 8 in 1 u/d
stream (30x2 PMTs)
1 x 48
1 board
2 boards
Drift chambers 1616 channels
2 x 48
Auxiliary devices 16 channels
1 x 48
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Type1
Type2
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Short summary

• Test of the board Type1 ? completed
• Test of the board Type2 ? completed
• System test ? completed
• Corrections and improvements
• One missing connection per board
• Control of the power up procedure
• Increased the read-out speed (50 events/s)
• Final PCB production in progress delivery
  confirmed for Feb. 10th 06
• Board mounting assigned company waiting for PCB
• Crates 6U (PSI), crate 9U (CAEN), interfaces
  ordered
• On-line PC (DAQ model) waiting
• Two test station are ready
• Firmware design in progress strongly dependent on
  PMT cabling
• Installation at PSI, together with the DAQ june
  06

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Auxiliary digitization
We consider useful exploiting the trigger FADC as
auxiliary digitazing system 100MHz, 10 bits, 5
?s depth, no fanin Two options are
considered Modified Type1 boards from 16 to 32
channels Requires manpower Use of the Type1
boards as they are, without mounting part of the
components Requires 2 crates both solutions have
the same cost
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DRS2 - new CMC card

• Better analog design (lower crosstalk and noise
• Moved chips more to front
• Dedicated clock input
• Dual FADC
• Temperature sensor
• 1k EEPROM
• 128 DRS2 channels ready

Noise level with the new CMC
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DRS2 - Clock nonlinearity
30ns
ns
bin
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DRS2 cell self-heating
Differential Pair
Vin
Vout
write
C
Ib/2
Ib/2
Ib

• Current depends on history of cell
• Quadratic effect
• Small below input voltage of 0.5V
• Solution OTA readout

-
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DRS2 - ghost pulses
signal
after one turn
after two turns
2
gt0.5
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DRS2 vs DRS3
Issue Solution DRS2 DRS3
Voltage nonlinearity Calibration with cubic splines in Front-end ?
Clock nonlinearity Time calibration frequency regulation ?
Cross talk 1 _at_ 7ns risetime Redesign of CMC card with ERNI 68-pin connector and interleaved ground lines ?
Temperature dependence - Calibration maybe possible to some extend- Keep electronics temperature constant- On-chip temperature compensation ?(?) ?
Self-heating of cells - Only use small signals (lt0.5 V)- On-chip temperature compensation (?) ?
Ghost pulses - Veto trigger 5us after cosmic or LED event- Veto trigger after other calorimeter hits?- Record 2us calorimeter history in each event?- Redesign sampling cell ? ?? ?
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DRS short summary

• DRS2 available for all experiment channels LXe,
  TC and DC
• DRS2 installation foreseen in june 2006
• Design of the DRS3 started (with the help of a
  new engineering )
• Solutions for the DRS2 problems were identified
• Replacement of part or all DRS2 with DRS3
  expected during 2007 beam shutdown

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DAQ

• Readout speed
• Struck SIS3100
• VPC board with CMC
• 2eVME transfer protocol
• Desktop PC (2.6 GHz P4)
• T 125us size/84 MB/sec
• 25 ms/event at full readout

• DAQ computers
• Producer www.thomas-krenn.com
• Cost 1800
• Hotplug cooler
• Redundant power supply
• Hot swap hard disks
• Remote management card

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Slow Control System - 2000

• Based on Midas Slow Control Bus
• Evolution of the SCS 1000
• Slow control of all MEG equipments
• 8 banks _at_ 8 In- or Outputs ? 64 I/O
• Each bank may contain
• Output 5V, 24V, 4-20mA, 10V, LED pulser
• Input 5V, 24V, 4-20mA, 10V, comparator
• Outputs stable during CPU software upgrade and
  reboot
• CPLD can be used for hard-wired logic ? control
  operation w/o CPU

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Conclusions of the last BVR

• An electronics integration scheme has been
  developed
• Minor details needs to be fixed done!
• All key electronics elements will be available
  before March 06 moved to June 06
• A test of the final electronics systems, together
  with crates, in magnetic field environment is
  planned in autumn done!

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Electronic chain
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DAQ and control
Ancillary system
3 crates
6 crates
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Rack space