ECE 444

1
ECE 444

• Session 7
• Dr. John G. Weber
• KL-241E
• 229-3182
• John.Weber_at_notes.udayton.edu
• jweber-1_at_woh.rr.com
• http//academic.udayton.edu/JohnWeber

2
More on Memories

• Verilog allows declaration of memory as an array
  of registers
• reg 310 memory031
• declares a memory of 31 32-bit words
• Quartus does support this declaration
• Quartus 9610 logic cells to build this register
  file

3
Example Memory Code

//reg_4_port //Quad port register file typical
for a general register file in a modern
computer module reg_4_port(Xin, Yin, Xaddr,
Yaddr, wx, wy, Aaddr, Baddr, setaddr,Aout, Bout,
clk, clr) input 310 Xin, Yin //data
ports for writing to the register file input
40 Xaddr, Yaddr, Aaddr, Baddr //address
ports for the register file input wx, wy, clk,
clr, setaddr output 321 Aout, Bout //data
output ports for reading from the register
file reg 310 REG 031 //register file
declaration reg 40 Xad, Yad, Aad,
Bad //registers to hold addresses reg 310
Aout, Bout //read data ports
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Example ( Cont)
always _at_(posedge clk) begin Xad lt
Xaddr Yad lt Yaddr Aad lt Aaddr Bad
lt Baddr Aout lt REGAad //always read from
Aout and Bout ports Bout lt REGBad if
(wx wy) //if writing to both ports, make sure
same address is not used begin if(XadYa
d) REGXaddrlt Xin else begin
REGXad lt Xin REGYad lt
Yin end end else begin if
(wx !wy) REGXad lt Xin if (wy
!wx) REGYad lt Yin end end endmod
ule
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Simulation
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Other Memory Structures

• Delay Lines
• Data enters one end and emerges at the other
  after a specified number of clocks
• FIFOs
• The first data written is the first one read
• LIFOs or Stacks
• The last data written is the first one read

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Digital Delay Line

• .
• .

• Specification
• Samples input in sequence immerge in sequence
  after a delay of n samples
• Let samples be 4-bit quantities
• Let delay be 4 samples

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Digital Delay Line
//fifo.v //a digital delay line module module
fifo(data_in, clk, data_out) parameter width
4, depth 4 input width-10 data_in input
clk output width-10 data_out reg
width-10 mem0depth-1 reg width-10
k reg width-10 data_out always _at_(posedge
clk) begin mem0 lt data_in for (k1
k lt depth kk1) begin memklt
memk-1 end data_out lt memdepth-1 end
endmodule
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Digital Delay Line Simulation
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First In First Out (FIFO) Memory
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First In First Out (FIFO) Memory
//fifo2.v //a fifo module / This module inserts
a value in the next available location, all data
is pulled from the bottom of the fifo. The
enqueue signal causes data to be inserted. The
dequeue pulls data from the bottom and moves the
remainder of the data down one position and
changes the value of the pointer to the next
available location/ module fifo2(data_in, clk,
enqueue, dequeue, data_out, memfull,
memempty) parameter width 4, depth
4 input width-10 data_in input clk,
enqueue, dequeue output width-10
data_out output memfull,memempty reg
width-10 mem0depth-1 reg width-10
k reg width-10 n1 reg width-10
data_out reg width-10 point 4'b1111 reg
memfull 0, memempty 1

• Specification
• First Data Word Inserted at Position N
• Data-In pointer adjusted to point to next
  available slot
• Data at Position N available at the output
• When data is removed from the FIFO, other data
  moves up to replace

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First In First Out (FIFO) Memory
always _at_(posedge clk) begin if (enqueue
!dequeue) if (point lt depth-1) for (n1
0 n1 lt depth-1 n1 n11) case
(point) n1begin memn1lt
data_in point lt point1 data_out
lt 0 memfull lt0 memempty
lt0 end endcase else if (point
depth-1) begin memdepth-1lt
data_in memfull lt 1 memempty lt
0 data_out lt 0 end
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First In First Out (FIFO) Memory
if (!enqueue dequeue) if
(point gt0) begin data_out lt mem0 point
lt point - 1 memfull lt 0 memempty lt
0 for (k0 k lt depth-1 kk1) begin me
mklt memk1 end memdepth-1 lt
0 end else begin data_out lt
mem0 memempty 1 memfull lt 0
end end endmodule
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Verilog Simulation for FIFO
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Stack (Last In First Out)
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Stack
//stack.v /This is a paramaterized stack
memory.When "push" is true, data at the input are
written to location 0 and the contents of the
memory are "pushed" down one location when the
clock transitions. When "pop" is true, the data
are moved up one location. The data at location
zero is removed from the stack. If the contents
of location depth-1 are non-zero and a push is
attempted, a stack overflow error is generated
and the data at the bottom of the stack appears
at data_bottom./ module stack(data_in, push,
pop, clk, data_out, data_bottom_out,
data_bottom_in, ovrflw) parameter width 4,
depth 4, depthcnt 2 //note 2depthcnt
depth input width-10 data_in,
data_bottom_in input push, pop, clk output
width-10 data_out, data_bottom_out output
ovrflw reg width-10 stack0depth-1 reg
width-10 data_out reg width-10
data_bottomr reg depthcnt-10 k reg
ovrflw wire width-10 DBRDBO always
_at_(posedge clk)
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Stack
begin if (push !pop) begin
if (stackdepth-1)
begin data_bottomr lt stackdepth-1 ovrflw
lt1 end else ovrflw lt
0 for (kdepth-1 k gt0 kk-1) stackk
lt stackk-1 stack0 lt data_in end
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Stack
if (!push pop) begin ovrflw lt
0 data_out lt stack0 for (k0 k lt
depth-1 k k1) stackk lt
stackk1 stackdepth-1
ltdata_bottomr data_bottomr lt
data_bottom_in end end assign DBRDBO
data_bottomr assign data_bottom_out
DBRDBO endmodule
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Stack Simulation
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Other Issues Inferred Latches in Synthesis

• Verilog will synthesize latches from conditional
  statements
• Occurs when all conditions are not specified
• May result in unintended behavior of circuit

//compute.v //example of inferred latches module
compute(marks, grade) input 30
marks output 10 grade reg 10
grade parameter FAIL 1, PASS 2, EXCELLENT
3 always _at_ (marks) if (marks lt 5) grade
FAIL else if ((marks gt5) (marks lt10)) grade
PASS endmodule
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Example Output
Undefined condition
Circuit sticks at last value, i.e. a latch
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Fixed Example

• Add explicit assignment

//compute.v //example of inferred latches module
compute(marks, grade) input 30
marks output 10 grade reg 10
grade parameter FAIL 1, PASS 2, EXCELLENT
3 always _at_ (marks) if (marks lt 5) grade
FAIL else if ((marks gt5) (marks lt10)) grade
PASS else grade EXCELLENT endmodule
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Fixed Example Results
Explicit values for all conditions
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Case Statements

• Same issue applies to use of case statements
• Specify all conditions to avoid latches

//stateupdate.v //example of inferred latches
with case statement module stateupdate(CurrentStat
e, Zip) input 10 CurrentState output 10
Zip reg 10 Zip parameter S0 0, S1 1,
S2 2, S3 3 always _at_(CurrentState) case
(CurrentState) S0, S3 Zip 0 S1 Zip
3 endcase endmodule
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Simulation Results
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Equations Generated
--A1L11 is 82 at LC3_6_A2 --operation mode is
normal A1L11 CurrentState1 !CurrentState0
A1L11 !CurrentState1 CurrentState0 --A1
L21 is 83 at LC5_6_A2 --operation mode is
normal A1L21 CurrentState1 !CurrentState0
A1L21 !CurrentState1 CurrentState0 --Cu
rrentState0 is CurrentState0 at
Pin_K11 --operation mode is input CurrentState0
INPUT() --CurrentState1 is CurrentState1
at Pin_C6 --operation mode is input CurrentState1
INPUT() --Zip0 is Zip0 at
Pin_E7 --operation mode is output Zip0
OUTPUT(A1L11) --Zip1 is Zip1 at
Pin_C8 --operation mode is output Zip1
OUTPUT(A1L21)
Latch
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Fixed Case Statement
//stateupdate.v //example of inferred latches
with case statement module stateupdate(CurrentStat
e, Zip) input 10 CurrentState output 10
Zip reg 10 Zip parameter S0 0, S1 1,
S2 2, S3 3 always _at_(CurrentState) begin
Zip 0 case (CurrentState) S0, S3 Zip
0 S1 Zip 3 endcase end endmodule
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Boolean Generated for Fixed Case
--A1L9 is 93 at LC3_6_A1 --operation mode is
normal A1L9 CurrentState0
!CurrentState1 --CurrentState0 is
CurrentState0 at Pin_B2 --operation mode is
input CurrentState0 INPUT() --CurrentState1
is CurrentState1 at Pin_C1 --operation mode is
input CurrentState1 INPUT() --Zip0 is
Zip0 at Pin_C2 --operation mode is
output Zip0 OUTPUT(A1L9) --Zip1 is Zip1
at Pin_C3 --operation mode is output Zip1
OUTPUT(A1L9)
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Simulation Results for Fixed Case
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Summary

• Specify all conditions to avoid latches
• Good idea in general
• Forces you to think about all aspects of design
• Forces a known, deterministic output
• Latches are not bad
• This discussion about avoiding unintentional ones
• Illustrations show who controls design
• You or the HDL compiler writer

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Project 2 Due 15 October 2003

• Goal
• Develop and demonstrate good design discipline
  and technique
• Practice design of memory circuits and
  controllers using Verilog HDL
• Project
• Design a Stack memory system with the following
  characteristics
• The top two locations of the stack are always
  available at two output ports
• A push command will put data at the input on
  the top of the stack and move everything else
  down one location
• A write_stack_0 command replaces the data on
  the top of the stack with the data at the input
  port
• A pop1 command removes the data from the top of
  the stack and moves everything else up one
  location
• A pop2 command removes the data from the top
  two locations in the stack and moves everything
  else up two locations
• An expansion port for the bottom of the stack
  which allows stack modules to be stacked.
• Implement as a parameterized design in terms of
  word length and the number of words in the stack.
  Hint Use small numbers for the parameters to
  speed compilation and ease testing the control
  logic.

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Project 3Due 10/22/2004

• Goal
• Develop and demonstrate good design discipline
  and technique
• Practice integration of circuits and controllers
  using Verilog HDL
• Project
• Design a system to test the ALU of project 1.
• Include a multi-port memory to hold the test data
  (initialize using a MIF).
• Display the output of the ALU on the 7-segment
  display of the NIOS development board.
• Use one of the user-programmable switches to
  initiate each cycle of the alu
• Use the DIP switch to select the ALU function.
• Provide the following
• Design document including a block diagram, brief
  description of your design, and a test plan
  (including rationale for the test data set)
• Results and conclusions (including selected
  screen captures of the simulation)
• Demonstration
• Electronic version of the project

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Project 4Due 10/29/2004

• Goal
• Develop and demonstrate good design discipline
  and technique
• Practice integration of communication circuits
  and controllers using Verilog HDL
• Project
• Design a RS-232 (comm port) interface and
  implement it on the NIOS development board.
• Provide the following
• Design document including a block diagram, brief
  description of your design, and a test plan
  (including rationale for the test data set)
• Results and conclusions (including selected
  screen captures of the simulation)
• Demonstration
• Electronic version of the project

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Final Project Due at the Final Exam Time

• Goal
• To integrate the knowledge gained from this
  course and others during your study.
• To consider factors other than technical ones in
  your design
• To work on a multidisciplinary project with a
  team (class will be formed into two teams for the
  final project)
• Project
• Propose your own projects (proposals due NLT 8
  October 2004)
• Develop a brief technical proposal for your
  project (constrained by the hardware we have
  available for prototyping (NIOS development
  board) and the software tools we have available
  (Visual Studio))
• Include your target application market and market
  analysis, packaging constraints (e.g. size,
  weight, and power) for your market area, any
  environmental considerations, and any ethical
  considerations. Typical areas that people have
  used in the past include 1) musical amplifier
  effects generator, 2) image processing hardware,
  and 3) special purpose digital processors.
• Include a realistic schedule for the development
  and test of your prototype

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Final Project Due at the Final Exam Time (cont)

• Report
• Formal technical report documenting your design,
  implementation and results. Include an economic
  analysis of your implementation, and outline what
  must be done to take your product to production.
• Formal technical presentation to the class during
  the final examination period. Outline your
  design and your results.
• Formal demonstration of your prototype to the
  class
• Summary of lessons learned from this project.