ECE 444

1
ECE 444

• Project and Assignment Update
• Dr. John G. Weber
• KL-241E
• 229-3182
• John.Weber_at_notes.udayton.edu
• jweber-1_at_woh.rr.com
• http//academic.udayton.edu/JohnWeber

2
Schedule of Projects and Assignments

• Project 2 (FIFO)Due 10/8/2004
• Project 3 (ALU Hardware)Due 10/22/2004
• Project 4 (RS-232) -- Due 10/29/2004
• Final Project Preliminary Design Review
  10/27/2004
• Final Project Interim Review Due 11/15/2004
• Final Project Final Presentation and
  Demonstration Due at Final Exam Time
• Assignment 5 (Digital Low Pass FIR IIR Filters)
  Due 10/15/2004
• Assignment 6 (Gausian Low Pass Filter) Due
  11/5/2004
• Assignment 7 (Optional for Extra
  CreditMultiplier) Due 11/12/2004

3
Project 2 Due 15 October 2003

• Goal
• Develop and demonstrate good design discipline
  and technique
• Practice design of memory circuits and
  controllers using Verilog HDL
• Project
• Design a Stack memory system with the following
  characteristics
• The top two locations of the stack are always
  available at two output ports
• A push command will put data at the input on
  the top of the stack and move everything else
  down one location
• A write_stack_0 command replaces the data on
  the top of the stack with the data at the input
  port
• A pop1 command removes the data from the top of
  the stack and moves everything else up one
  location
• A pop2 command removes the data from the top
  two locations in the stack and moves everything
  else up two locations
• An expansion port for the bottom of the stack
  which allows stack modules to be stacked.
• Implement as a parameterized design in terms of
  word length and the number of words in the stack.
  Hint Use small numbers for the parameters to
  speed compilation and ease testing the control
  logic.

4
Project 3Due 10/22/2004

• Goal
• Develop and demonstrate good design discipline
  and technique
• Practice integration of circuits and controllers
  using Verilog HDL
• Project
• Design a system to test the ALU of project 1.
• Include a multi-port memory to hold the test data
  (initialize using a MIF).
• Display the output of the ALU on the 7-segment
  display of the NIOS development board.
• Use one of the user-programmable switches to
  initiate each cycle of the alu
• Use the DIP switch to select the ALU function.
• Provide the following
• Design document including a block diagram, brief
  description of your design, and a test plan
  (including rationale for the test data set)
• Results and conclusions (including selected
  screen captures of the simulation)
• Demonstration
• Electronic version of the project

5
Project 4Due 10/29/2004

• Goal
• Develop and demonstrate good design discipline
  and technique
• Practice integration of communication circuits
  and controllers using Verilog HDL
• Project
• Design a RS-232 (comm port) interface and
  implement it on the NIOS development board.
• Provide the following
• Design document including a block diagram, brief
  description of your design, and a test plan
  (including rationale for the test data set)
• Results and conclusions (including selected
  screen captures of the simulation)
• Demonstration
• Electronic version of the project

6
Final Project Preliminary Design Review 10/27/2004

• 10 15 minute presentation using power point
  (use memory stick or CD or e-mail to me)
• Content
• Background on proposed product
• Market Analysis
• Proposed Package (size, weight, power, cooling,
  etc)
• Block Diagram
• Technical Discussion
• Technical Issues
• Schedule

7
Final Project Interim Review Due 11/15/2004

• Design Discussion
• Technical Issues
• Test Approach
• Demonstration Plan

8
Final Project Due at the Final Exam Time

• Goal
• To integrate the knowledge gained from this
  course and others during your study.
• To consider factors other than technical ones in
  your design
• To work on a multidisciplinary project with a
  team (class will be formed into two teams for the
  final project)
• Project
• Propose your own projects (proposals due NLT 8
  October 2004)
• Develop a brief technical proposal for your
  project (constrained by the hardware we have
  available for prototyping (NIOS development
  board) and the software tools we have available
  (Visual Studio))
• Include your target application market and market
  analysis, packaging constraints (e.g. size,
  weight, and power) for your market area, any
  environmental considerations, and any ethical
  considerations. Typical areas that people have
  used in the past include 1) musical amplifier
  effects generator, 2) image processing hardware,
  and 3) special purpose digital processors.
• Include a realistic schedule for the development
  and test of your prototype

9
Final Project Due at the Final Exam Time (cont)

• Report
• Formal technical report documenting your design,
  implementation and results. Include an economic
  analysis of your implementation, and outline what
  must be done to take your product to production.
• Formal technical presentation to the class during
  the final examination period. Outline your
  design and your results.
• Formal demonstration of your prototype to the
  class
• Summary of lessons learned from this project.

10
Assignment 5Due 10/15/2004

• Goal Provide practice in digital filter design
  and implementation
• Reading Text page 591-613
• Problem Using MATLAB, design low pass FIR and
  IIR filters with the following characteristics
• Cutoff Frequency 2000 Hz, Pass-band Gain 0
  db, stop-band attenuation 20db, Sampling Rate
  10 KHz
• The input data path is 8 bits wide and the
  coefficients are to be stored as 10 bit values.
• Plot the impulse and step response of your
  filters
• Develop a verilog design and simulate the
  filters impulse and step response

11
Assignment 6 Due 11/5/2004

• Goal Practice Implementation of Digital
  Filters. Implement from scratch and using
  library modules.
• Problem Consider the Gaussian_Low-Pass FIR
  Filter Example in the text (pg 599).
• Develop a MATLAB simulation for this filter and
  plot the impulse and step response.
• Implement the filter design from the text adding
  scaling to keep the input and output ranges
  consistent
• Create a digital filter stage module
  incorporating a shift register stage, a
  multiplier, and an adder and re-implement the
  filter using multiple instances of your module.
• Examine the Quartus library modules and see if
  any approximate your module design
• Select library module(s) and re-implement the
  filter
• Verify that your results are consistent with the
  MATLAB simulation

12
Assignment 7 (Optional -- Extra Credit)Due
11/12/2004

• Goal Develop familiarity with hardware
  multipliers and practice implementing them
• Problem
• Extend the unsigned multiplier to handle unsigned
  numbers of eight bits
• Develop the verilog code and simulate
• Extend the eight bit multiplier to handle signed
  numbers
• Develop the verilog code and simulate
• Build an eight-bit multiplier using the LPM-Mult
  function available in Quartus. Compare its
  performance to your designs.