ECE 444

1
ECE 444

• Session 5
• Dr. John G. Weber
• KL-241E
• 229-3182
• John.Weber_at_notes.udayton.edu
• jweber-1_at_woh.rr.com
• http//academic.udayton.edu/JohnWeber

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Combinatorial Logic Blocks

• Multiplexers
• Used to steer data
• Suppose we want the output of a circuit, D, to be
  equal to the input A if a select signal is false
  and equal to the input B if the select signal is
  true
• This circuit is a two-input, one-bit multiplexer
  which steers the data to the D input of a
  flip-flop

3
Verilog for 2-input mux
//mux_2in_1b.v //a two input, one-bit mux module
mux_2in_1b(d, a, b, sel) input a, b, sel output
d assign d a !sel b sel endmodule
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Multiplexers

• Extend this to a two-input, n-bit multiplexer

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Verilog for n-bit mux
//mux_2in_nb.v //parameterized, n-bit mux module
mux_2in_nb(D, A, B, sel) parameter width
4 input width-10 A, B input sel output
width-10 D reg width-10 D always _at_(sel or
A or B) if (sel) D B else D A endmodule
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Behavioral Modeling Styles

• Continuous Assignment Models
• Used in the full-adder
• Data Flow Models
• Concurrent continuous assignment or asynchronous
  cyclic behavior
• Algorithm Based Models
• Abstract Model of behavior

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Continuous Assignment Model

• Consider a Simple Comparator
• compares two vectors and returns A.lt.B, A.gt. B,
  or A B
• Verilog

//compare_4.v //4-bit comparator module
compare_4(A_lt_B, A_gt_B, A_eq_B, A, B) input
30 A, B output A_lt_B, A_gt_B, A_eq_B assign
A_lt_B (A lt B) assign A_gt_B (A gt B) assign
A_eq_B (A B) endmodule
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Parameterized Compare Module

• Since the logic does not depend on the size of
  the vectors being compared, we can easily convert
  this to a parameterized module.

//compare_param_16.v //16-bit parameterized
comparator module compare_param_16 (A_lt_B,
A_gt_B, A_eq_B, A, B) parameter width
16 input width-10 A, B output A_lt_B,
A_gt_B, A_eq_B assign A_lt_B (A lt B) assign
A_gt_B (A gt B) assign A_eq_B (A
B) endmodule
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Data Flow Model

• Model with cyclic behavior
• Use always construct

//compare_4.v //4-bit comparator module
compare_4(A_lt_B, A_gt_B, A_eq_B, A, B) input
30 A, B output A_lt_B, A_gt_B, A_eq_B always
_at_(A or B) begin A_lt_B (A lt B) A_gt_B (A gt
B) A_eq_B (A B) end endmodule
Note Procedural assignment operator, , is
called a blocking assignment and statements are
executed in order.
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Data Flow Model (Cont.)

• Consider a 4-bit shift register (see fig 5-7)
• Flip-flops labeled (left to right) D, C, B, A
• Verilog Code

//shiftright_4.v module shiftright_4(E, D, C, B,
A, clk, rst) output A input E, clk, rst reg A,
B, C, D always _at_(posedge clk or posedge
rst) begin if (rst) begin A 0 B 0 C 0 D
0 end else begin A B B C C D D
E end end endmodule
Blocking assignment
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Data Flow Model (Cont.)

• To see effect of blocking assignment, reverse
  order of register assignment statements

//shiftright_4.v module shiftright_4(E, D, C, B,
A, clk, rst) output A input E, clk, rst reg A,
B, C, D always _at_(posedge clk or posedge
rst) begin if (rst) begin A 0 B 0 C 0 D
0 end else begin D E //A B C D //B
C B C //C D A B //D
E end end endmodule
Blocking assignment causes D to have contents of
E, then C to receive contents of D, then B to
receive contents of C and finally A to receive
contents of B on the same clock edge.
Degenerates into a single bit register.
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Non-Blocking Assignment

• Non-blocking assignment all assignment statements
  execute concurrently
• Use non-blocking assignment operator lt

//shiftright_4.v module shiftright_4(E, D, C, B,
A, clk, rst) output A input E, clk, rst reg A,
B, C, D always _at_(posedge clk or posedge
rst) begin if (rst) begin A 0 B 0 C 0 D
0 end else begin D lt E //A lt B C lt
D //B lt C B lt C //C lt D A lt B //D lt
E end end endmodule
Either order is fine and results in the desired
4-bit shift register
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Algorithm Based-Model

• Describes function of module using an algorithm
• Looks more like software but beware

//compare_algo_4.v //4-bit comparator using an
algorithm module compare_algo_4(A_lt_B, A_gt_B,
A_eq_B, A, B) input 30 A, B output A_lt_B,
A_gt_B, A_eq_B reg A_lt_B, A_gt_B,
A_eq_B always _at_(A or B) begin A_lt_B
0 //initialize outputs A_gt_B 0 A_eq_B 0 if
(A B) A_eq_B 1 else if (A gt B) A_gt_B
1 else A_lt_B 1 end endmodule
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Sequential Circuits

• Use language features discussed last time to
  design sequential circuits
• Discuss each feature as we use it in a series of
  examples
• Sequential Circuit Block Diagram
• Memory used to track the state of the circuit
• Combinatorial logic used to determine next state
  as a function of inputs and current state
• Combinatorial logic also used to derive output
  functions

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Classical Tools for Sequential Circuit Design

• State Diagram
• Provides a diagram of the available states, the
  conditions for switching states and the output at
  each state
• State Table
• Provides a tabular (truth table like) view of the
  states and the logic required
• Algorithmic-State Machine (ASM) Charts (Ch 5 in
  text)
• Flow chart type of presentation for finite state
  machines
• Register Transfer Language
• Provides a sequential language description of the
  inputs, outputs and next state requirement

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Example Sequential Circuit Requirement

• Problem
• Design a circuit that monitors a serial input and
  detects a string of three or more contiguous
  ones. When three or more ones are detected in
  a row, generate a one on the output line.

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State Diagram
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State Table
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ASM Chart
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Register Transfer Language
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Verilog HDL
//seq_detect.v //sample sequential machine to
detect a sequence of three ones in a serial //bit
stream. module seq_detect (x, y, clk, rst,
state) input x, clk, rst output y output
10 state reg y reg 10 state parameter
S0 2'b00, S1 2'b01, S2 2'b10, S3 2'b11
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Verilog HDL(cont)
always _at_ (posedge clk or negedge rst) if (rst)
begin state S0 y0
end else case (state) S0 begin y 0
if(x) state S1 else state S0 end S1
if(x) state S2 else state S0 S2 if(x)
state S3 else state S0 S3 begin
y 1 if(x) state
S3 else state S0
end endcase endmodule
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Simulation
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Finite State Machine Types

• Two typesMealy and Moore
• Which was the Example?

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Assignment 3 Due Wednesday 9/15/2004

• Goal
• Practice in Verilog continuous and procedural
  assignments
• Practice in Verilog module design.
• Problems
• Include a design specification and a structure
  description for each problem
• Develop a verilog module and simulation for each
  problem

• Design a 4-bit encoder
• Design a 4-input priority encoder
• Design a 8-input majority function (output is one
  if five or more inputs are asserted
• Problem 1page 100
• Problem 2 page 101

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Project 1 Due 2 October 2004

• Goal
• Develop and demonstrate good design discipline
  and technique
• Practice design of combinatorial logic circuits
  using Verilog HDL
• Project
• Develop 8-bit, twos complement arithmetic ALU
  with data inputs A70 and B70 which performs
  the following operations asynchronously
• A B
• A B
• B A
• A OR B
• A AND B
• A XOR B
• NOT A
• NOT B
• - A
• - B
• For each function above, provide the following
  outputs
• A gt B
• A lt B
• A B