Title: FPGA Based Fuzzy Logic Controller for SemiActive Suspensions
1FPGA Based Fuzzy Logic Controller for Semi-Active
Suspensions
2Outline
- Types of Suspension Systems
- Project Objective
3DSP and Reconfigurable Computing Systems
4Outline
- What is DSP?...
- Implementation of Various Algorithms
- Advantages of FPGA in DSP
- Tools available/Mapping DSP onto FPGA
5Resources
- 1 A Primer on FPGA-Based DSP Applications, by
Acromag Inc. - 2 Designing Digital Signal Processing with
FPGAs, by Allen Kinast - 3 FPGA Implementations of Fast Fourier
Transforms for Real-Time Signal and Image
Processing, by I.S. Uzun, A. Amira and A.
Bouridane - 4 Choosing the Right Architecture for
Real-Time Signal Processing Designs, by Leon
Adams. - 5 Digital Signal Processors Applications and
Architectures, by Kurt Keutzer
6What is DSP?
- Concerned with the manipulation of signals for
- Filtering
- Transformation
- Decoding/Encoding etc.
- Widely implemented in PDSP
7DSP Applications
- Wireless Communication
- Audio Applications
- Image Processing/Medical Imaging
- Networking
- Weather forecasting
8Various Algorithms
- Finite Impulse Response (FIR) filters
- Fast Fourier Transforms (FFT)
- Infinite Impulse Response (IIR) filters
- Forward Error Correction (FEC)
- Modulation/Demodulation
9DSP Implementation Comparison
Most suitable technology??
10PDSP vs. FPGA
- PDSP
- Specialized microprocessor based on the Von
Neumann arch. - Programmed in C/assembly for performance
- Suited for complex math-intensive tasks, with
conditional processing. - Limited in performance by the clock rate and
number of operations it can perform per clock
cycle. - e.g. TMS320C6201 has 2 multipliers 200MHz clock
? 400M multipliers/second
11PDSP vs. FPGA cont.
- FPGA
- Uncommitted gates
- Programmed by HDL.
- Performance limited by the number of gates and
clock rate. - Suited for a wide range of applications
12Advantages/Disadvantages of FPGA
- Advantages
- Parallel Processing (Performance)
- Flexible Architecture
- Price
- Power Demand compared to DSP
- Disadvantages
- Higher development cost and increased time to
market than DSP - Implementation of conditional processing
13Important Building Blocks
- Add
- Subtract
- Multiply
- Multiply and Add
- Multiply and Accumulate (MAC) Unit
14256 Tap FIR Filter
Conventional DSP Serial processing
256 Loops needed to process samples 1 FIR tap per
DSP instruction cycle
15256 Tap FIR Filter cont.
FPGA Parallel processing
All 256 MAC operations in 1 clock cycle
16FPGA Design Flexibility
Multiply and Add
FPGA Design Optimization
Parallel
Semi-Parallel
Serial
D Q
Q (A x B) (C x D) (E x F) (G x H)
Cost
Speed
17Performance of PDSP VS. FPGA
18Advanced FPGA Architectures with DSP Resources
19DSP Design tools
- C, C
- MATLAB / Simulink
- HDL (VHDL / Verilog)
- Xilinx EDK/ISE
20MATLAB / Simulink
21Simulink
22Simulink ISE
23Design flow with FPGA
24DSP Design Evolution from HW DSP to FPGA DSP
solutions
- Signal capture and sync.
- Data exchange methodology
- off-the shelf hardware
- Logic Processing
- Price/Feature
- Data/Sample rates
- Debugging
- Use of IP cores
- I/O interface
- Development cycles
- Deployment cost
25Conclusion
- The primary reason solutions were so expensive
to design, slow to develop and prove, and
difficult to re-deploy was that the solutions
were fixed in hardware 1
26Questions?