CSE 144 Project

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CSE 144 Project
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Overall Goal of the Project

• Implement a physical design tool for a two-row
  standard cell design

0
5
3
1
2
4
3
Problems to be resolved

• Positions of components
• Which row to place each component Partitioning
• The relative position of components in each row
  Placement
• Interconnect between components Routing

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What to optimize?

• In partitioning minimize the number of
  interconnects between partitions (rows)
• In placement minimize the overall horizontal
  length of interconnects
• In routing fulfill the geometrical constraints
  --- wires in the same directions should not
  overlap

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Input Specification

• Matrix form circuit model
• First line the number of components, N
• The following N lines the output-input
  connections between components
• A non-zero entry Aij denotes a connection between
  components i and j
• The value of Aij denotes the pin number of i
• Last line the size of each components

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Output Specification
Partitioning Placement

• Routing
• Position of pins connected by each net
• Leftmost and rightmost boundaries of each nets
• Channel track occupied by each net

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Part 1 Partitioning

• Goal minimize the number of interconnects
  crossing the two rows
• Constraints partition size should stay within a
  tolerance window
• The tolerance bound is the size of the largest
  component
• floor(V/2 - Cmax) lt A lt ceiling( V/2
  Cmax)

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Fundamental Ideas

• The flow of FM algorithm is the same as KL
  algorithm
• Two differences
• KL component swap per tentative move FM one
  component per tentative move
• KL any pair of unlocked components valid FM
  only allow moves fulfilling area constraints

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Algorithm

• Initial partitioning (subject to area
  constraints)
• Gain calculation (same equations as in KL)
• Move and lock the component with highest gain,
  which satisfies area constraints (one component
  per tentative move). Update gains.
• Repeat moving until no one can be moved
• Make permanent all the movements up to and
  including the move giving the highest
  accumulative gain
• Unlock all components and repeat until no
  improvement can be obtained

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How to improve efficiency?

• Gain updating technique
• Locked components neednt be updated
• Components unconnected to the ones being moved
  neednt be updated
• Use efficient data structure
• Three data structure candidates provided

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Data Structure 1 Linked List
Gain stamps
Unlocked components
Gmax
Current max gain
3
Comp 5
Comp 0
NIL
2
Comp 1
Comp 3
NIL
1
0
Comp 4
NIL
-1

• Always choose component in the highest linked
  list for tentative move
• Gain updating corresponds to changing the
  position of components in the linked lists

-2
-3
-Gmax
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Data Structure 2 Gain Matrix
Components
c4
c0
c2
c3
c5
c1
1
1
3

• Always choose component in the highest row that
  contains 1-entries
• Gain updating corresponds to changing the
  positions of 1-entries in the gain matrix

1
1
2
1
Gain value
1
0
1
-1
-2
-3
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Data Structure 3 Gain Array
Components
c1
c2
c3
c4
c5
c0
3
2
-1
2
0
3
Gain

• Gain updating corresponds to changing the values
  of the gain array elements

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Implementation Requirement

• Analyze the suggested data structures in terms of
• Primarily computational efficiency
• Secondarily space efficiency
• Implement the most efficient one you think
• Provide a detailed description of your analysis
  in your turn-in