CPSC 161 Lecture 6

1
CPSC 161Lecture 6

• Prof. L.N. Bhuyan
• http//www.cs.ucr.edu/bhuyan/cs161/index.html

2
Numbers

• Bits are just bits (no inherent meaning)
  conventions define relationship between bits and
  numbers
• Binary numbers (base 2) 0000 0001 0010 0011 0100
  0101 0110 0111 1000 1001... decimal 0...2n-1
• Of course it gets more complicated numbers are
  finite (overflow) fractions and real
  numbers negative numbers e.g., no MIPS subi
  instruction addi can add a negative number
• How do we represent negative numbers? i.e.,
  which bit patterns will represent which numbers?

3
Possible Representations

• Sign Magnitude One's Complement
  Two's Complement 000 0 000 0 000
  0 001 1 001 1 001 1 010 2 010
  2 010 2 011 3 011 3 011 3 100
  -0 100 -3 100 -4 101 -1 101 -2 101
  -3 110 -2 110 -1 110 -2 111 -3 111
  -0 111 -1
• Issues balance, number of zeros, ease of
  operations
• Which one is best? Why?

4
MIPS

• 32 bit signed numbers0000 0000 0000 0000 0000
  0000 0000 0000two 0ten0000 0000 0000 0000 0000
  0000 0000 0001two 1ten0000 0000 0000 0000
  0000 0000 0000 0010two 2ten...0111 1111
  1111 1111 1111 1111 1111 1110two
  2,147,483,646ten0111 1111 1111 1111 1111 1111
  1111 1111two 2,147,483,647ten1000 0000 0000
  0000 0000 0000 0000 0000two
  2,147,483,648ten1000 0000 0000 0000 0000 0000
  0000 0001two 2,147,483,647ten1000 0000 0000
  0000 0000 0000 0000 0010two
  2,147,483,646ten...1111 1111 1111 1111 1111
  1111 1111 1101two 3ten1111 1111 1111 1111
  1111 1111 1111 1110two 2ten1111 1111 1111
  1111 1111 1111 1111 1111two 1ten

5
Two's Complement Operations

• Negating a two's complement number invert all
  bits and add 1
• remember negate and invert are quite
  different!
• Converting n bit numbers into numbers with more
  than n bits
• MIPS 16 bit immediate gets converted to 32 bits
  for arithmetic
• copy the most significant bit (the sign bit) into
  the other bits 0010 -gt 0000 0010 1010 -gt
  1111 1010
• "sign extension" (lbu vs. lb)

6
Addition Subtraction

• Just like in grade school (carry/borrow 1s)
  0111 0111 0110  0110 - 0110 - 0101
• Two's complement operations easy
• subtraction using addition of negative numbers
  0111  1010
• Overflow (result too large for finite computer
  word)
• e.g., adding two n-bit numbers does not yield an
  n-bit number 0111  0001 note that overflow
  term is somewhat misleading, 1000 it does not
  mean a carry overflowed

7
MIPS ALU Instructions

• Add, AddU, Sub, SubU, AddI, AddIU
• gt 2s complement adder/sub with overflow
  detection
• And, Or, AndI, OrI, Xor, Xori, Nor
• gt Logical AND, logical OR, XOR, nor
• SLTI, SLTIU (set less than)
• gt 2s complement adder with inverter, check sign
  bit of result

8
MIPS arithmetic instruction format
31
25
20
15
5
0
R-type
op
Rs
Rt
Rd
funct
I-Type
op
Rs
Rt
Immed 16
Type op funct ADDI 10 xx ADDIU 11 xx SLTI 12 xx SL
TIU 13 xx ANDI 14 xx ORI 15 xx XORI 16 xx LUI 17 x
x
Type op funct ADD 00 40 ADDU 00 41 SUB 00 42 SUBU
00 43 AND 00 44 OR 00 45 XOR 00 46 NOR 00 47
Type op funct 00 50 00 51 SLT 00 52 SLTU 00 53
9
Refined Requirements
(1) Functional Specification inputs 2 x 32-bit
operands A, B, 4-bit mode outputs 32-bit result
S, 1-bit carry, 1 bit overflow operations add,
addu, sub, subu, and, or, xor, nor, slt,
sltU (2) Block Diagram
32
32
A
B
4
ALU
m
c
ovf
S
32
10
Refined Diagram bit-slice ALU
32
A
B
32
4
M
Ovflw
32
S

• Co a.b a.Cin b.Cin
• Sum

11
Seven plus a MUX ?

• Design trick 2 take pieces you know (or can
  imagine) and try to put them together
• Design trick 3 solve part of the problem and
  extend

S-select
CarryIn
and
A
or
Result
Mux
add
B
CarryOut
12
Additional operations

• A - B A ( B)
• form two complement by invert and add one

S-select
CarryIn
invert
and
A
or
Result
Mux
add
1-bit Full Adder
B
CarryOut
Set-less-than? left as an exercise
13
Detecting Overflow

• No overflow when adding a positive and a negative
  number
• No overflow when signs are the same for
  subtraction
• Overflow occurs when the value affects the sign
• overflow when adding two positives yields a
  negative
• or, adding two negatives gives a positive
• or, subtract a negative from a positive and get a
  negative
• or, subtract a positive from a negative and get a
  positive
• Consider the operations A B, and A B
• Can overflow occur if B is 0 ?
• Can overflow occur if A is 0 ?

14
Effects of Overflow

• An exception (interrupt) occurs
• Control jumps to predefined address for exception
• Interrupted address is saved for possible
  resumption
• Details based on software system / language
• example flight control vs. homework assignment
• Don't always want to detect overflow new MIPS
  instructions addu, addiu, subu note addiu
  still sign-extends! note sltu, sltiu for
  unsigned comparisons

15
Overflow Detection

• Overflow the result is too large (or too small)
  to represent properly
• Example - 8 lt 4-bit binary number lt 7
• When adding operands with different signs,
  overflow cannot occur!
• Overflow occurs when adding
• 2 positive numbers and the sum is negative
• 2 negative numbers and the sum is positive
• On your own Prove you can detect overflow by
• Carry into MSB Carry out of MSB

1
1
1
0
1
0
0
1
1
1
1
1
0
0
7
4
3
5
0
0
1
1

1
0
1
1

1
0
1
0
0
1
1
1
6
7
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Overflow Detection Logic

• Carry into MSB Carry out of MSB
• For a N-bit ALU Overflow CarryInN - 1 XOR
  CarryOutN - 1

CarryIn0
A0
1-bit ALU
Result0
X
Y
X XOR Y
B0
0
0
0
CarryOut0
0
1
1
1
0
1
1
1
0
CarryIn2
A2
1-bit ALU
Result2
B2
CarryIn3
Overflow
A3
1-bit ALU
Result3
B3
CarryOut3
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But What about Performance?

• Critical Path of n-bit Rippled-carry adder is nCP

CarryIn0
A0
1-bit ALU
Result0
B0
CarryOut0
CarryIn1
A1
1-bit ALU
Result1
B1
CarryOut1
CarryIn2
A2
1-bit ALU
Result2
B2
CarryOut2
CarryIn3
A3
1-bit ALU
Result3
B3
CarryOut3
Design Trick throw hardware at it
18
Carry Look Ahead (Design trick peek)
Cin
A B C-out 0 0 0 kill 0 1 C-in propagate 1 0 C-
in propagate 1 1 1 generate
A0
S
G
B1
P
C1 G0 C0 P0
P A and B G A xor B
A
S
G
B
P
C2 G1 G0 P1 C0 P0 P1
A
S
G
B
P
C3 G2 G1 P2 G0 P1 P2 C0 P0 P1
P2
A
S
G
G
B
P
P
C4 . . .
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Cascaded Carry Look-ahead (16-bit) Abstraction
C0
G0
P0
C1 G0 C0 P0
C2 G1 G0 P1 C0 P0 P1
C3 G2 G1 P2 G0 P1 P2 C0 P0 P1
P2
G
P
C4 . . .
20
Additional MIPS ALU requirements

• Mult, MultU, Div, DivU (next lecture)gt Need
  32-bit multiply and divide, signed and unsigned
• Sll, Srl, Sra (next lecture)gt Need left shift,
  right shift, right shift arithmetic by 0 to 31
  bits
• Nor (leave as exercise to reader)gt logical NOR
  or use 2 steps (A OR B) XOR 1111....1111

21
Multiplication

• More complicated than addition
• accomplished via shifting and addition
• More time and more area
• Let's look at 3 versions based on a gradeschool
  algorithm 0010 (multiplicand) __x_101
  1 (multiplier)
• Negative numbers convert and multiply
• there are better techniques, we wont look at them

22
Multiplication Implementation
Datapath
Control
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Final Version

• Multiplier starts in right half of product

What goes here?
24
Floating Point (a brief look)

• We need a way to represent
• numbers with fractions, e.g., 3.1416
• very small numbers, e.g., .000000001
• very large numbers, e.g., 3.15576 109
• Representation
• sign, exponent, significand (1)sign
  significand 2exponent
• more bits for significand gives more accuracy
• more bits for exponent increases range
• IEEE 754 floating point standard
• single precision 8 bit exponent, 23 bit
  significand
• double precision 11 bit exponent, 52 bit
  significand

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IEEE 754 floating-point standard

• Leading 1 bit of significand is implicit
• Exponent is biased to make sorting easier
• all 0s is smallest exponent all 1s is largest
• bias of 127 for single precision and 1023 for
  double precision
• summary (1)sign (1significand)
  2exponent bias
• Example
• decimal -.75 - ( ½ ¼ )
• binary -.11 -1.1 x 2-1
• floating point exponent 126 01111110
• IEEE single precision 10111111010000000000000000
  000000

26
Floating point addition

27
Floating Point Complexities

• Operations are more complicated (see text)
• In addition to overflow we can have underflow
• Accuracy can be a big problem
• IEEE 754 keeps two extra bits, guard and round
• four rounding modes
• positive divided by zero yields infinity
• zero divide by zero yields not a number
• other complexities
• Implementing the standard can be tricky
• Not using the standard can be even worse
• see text for description of 80x86 and Pentium bug!

28
Chapter Three Summary

• Computer arithmetic is constrained by limited
  precision
• Bit patterns have no inherent meaning but
  standards do exist
• twos complement
• IEEE 754 floating point
• Computer instructions determine meaning of the
  bit patterns
• Performance and accuracy are important so there
  are many complexities in real machines
• Algorithm choice is important and may lead to
  hardware optimizations for both space and time
  (e.g., multiplication)
• You may want to look back (Section 3.10 is great
  reading!)