Sequential logic circuits

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Sequential logic circuits
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Outline

• Sequential Circuit Models
• Asynchronous
• Synchronous
• Latches
• Flip-Flops

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Sequential logic circuits

• The main characteristic of combinational logic
  circuits is that their output values depend on
  their present input values.
• Sequential logic circuits differ from
  combinational logic circuits because they contain
  memory elements so that their output values
  depend on both present and past input values

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Sequential logic circuits

• Sequential circuits can be Asynchronous or
  synchronous.
• Asynchronous sequential circuits change their
  states and output values whenever a change in
  input values occurs.
• Synchronous sequential circuits change their
  states and output values at fixed points of time,
  i.e. clock signals.

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Sequential Circuit Models
Universal model
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Combinational circuit model
Mealy machine model
Moore machine model
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Sequential Circuit Models
Circuit type Excitation Output
Combinational None O g(I)
Moore Machine E f (I, St) O g(St)
Mealy Machine E f (I, St) O g(I, St)
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Memory Devices

• Latches A latch is a memory element whose
  excitation signals control the state of the
  device. A latch has two stages set and reset. Set
  stage sets the output to 1. Reset stage set the
  output to 0.
• Flip-flops A flip-flop is a memory device that
  has clock signals control the state of the
  device.

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Latch
Flip-flop
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Latch and Flip-Flop Devices
Device of Elements Description
74LS73A 2 Negative-edge triggered JK flip-flop with clear
7474 2 Positive-edge triggered D flip-flop with preset and clear
74LS75 4 D Latch with enable
7476 2 Pulse-edge triggered JK flip-flop with preset and clear
74111 2 Master-slave JK flip-flop with preset, clear, and data lock out
74116 2 4-bit hazard-free D latch with clear and dual enable
74175 4 Positive-edge triggered D flip-flop with clear
74273 8 Positive-edge triggered D flip-flop with clear
74276 4 Negative-edge triggered JK flip-flop with preset and clear
74279 4 SR latch with active-low inputs
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Inverter Chains
Ring oscillator
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Latches

• RS Latch
• The RS latch is the basic memory element consists
  of two cross-coupled NOR gates. It has two input
  signals, S set signal and R reset signal. It
  also has two outputs Q and Q' and two states, a
  set state when Q 1 and a reset state when Q 0
  (Q' 1)

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S R Q Q'
1 0 1 0
0 0 1 0
0 1 0 1
0 0 0 1
1 1 0 0
S R Q
0 0 hold
0 1 0 reset
1 0 1 set
1 1 unstable
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Theoretical state diagram of cross-coupled NOR
gates
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Observed state diagram of cross-coupled NOR gates
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RS Latch excitation table
S R Q(t) Q(t1)
0 0 0 0 Hold
0 0 1 1 Hold
0 1 0 0 Reset Q(t1) S(t) R'(t)Q(t)
0 1 1 0 Reset Q(t1) S(t) R'(t)Q(t)
1 0 0 1 Set Q S R'Q
1 0 1 1 Set Q S R'Q
1 1 0 X Forbidden
1 1 1 X Forbidden
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S R Q Q'
1 0 1 0
1 1 1 0
0 1 0 1
1 1 0 1
0 0 1 1
S R Q
0 0 unstable
0 1 0 reset
1 0 1 set
1 1 hold
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State, Clock, Setup Time, and Hold Time

• The Clocking event can be either from low to high
  or from high to low. The input signal around
  clocking event must remain unchanged in order to
  have a correct effect on the outcome of the new
  state.
• Tsu the minimum time interval preceding
• the clocking event during the input signal
• must remain unchanged
• Th the minimum time interval after edge
• of the clocking event during the input signal
  
• must remain unchanged

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Timing Diagram of RS-Latch
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JK Latch
S R Q(t) Q(t1)
0 0 0 0 Hold
0 0 1 1 Hold
0 1 0 0 Reset
0 1 1 0 Reset
1 0 0 1 Set Q K'Q JQ'
1 0 1 1 Set Q K'Q JQ'
1 1 0 1 toggle
1 1 1 0 toggle
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Level-Sensitive Latches
A level-sensitive latch is a latch with an
additional enable input. RS latch
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RS Latch with Enable
C S R Q(t) Q(t1)
0 X X 0 0 Hold
0 X C 1 1 Hold
1 0 0 0 0 Hold
1 0 0 1 1 Hold
1 0 1 0 0 Reset
1 0 1 1 0 Reset
1 1 0 0 1 Set
1 1 0 1 1 Set
1 1 1 0 1 toggle
1 1 1 1 0 toggle
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D Latch
C D Q(t) Q(t1)
0 X 0 0 Hold
0 X 1 1 Hold
1 0 0 0 Reset
1 0 1 0 Reset
1 1 0 1 Set
1 1 1 1 Set
Q D
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Flip-Flops
A flip-flop is a level-sensitive latch with a
clock input. RS flip-flop
Q S R'Q
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T (Toggle) flip-flop
D Q(t) Q(t1)
0 0 0 Hold
0 1 1 Hold
1 0 1 Toggle
1 1 0 Toggle
Q TQ' T'Q
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Master Slave Flip-Flops
A master slave flip-flop consists of two latches
and an inverter. Master-slave RS flip-flop
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Master-Slave JK Flip-Flops
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Positive Edge-Triggered Flip-Flops
Positive edge-triggered RS flip-flop timing
diagram
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Positive edge-triggered JK flip-flop timing
diagram
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Positive edge-triggered D flip-flop timing
diagram
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Positive Edge-Triggered Timing
A circuit that generates a positive
edge-triggered timing signal can be constructed
as follows
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Type When inputs are sampled When outputs are valid
Unclocked latch Always Propagation delay from input change
Level-sensitive latch Clock high Propagation delay from input change
Positive-edge latch Clock low-to-high transition Propagation delay from rising edge of clock
Negative-edge latch Clock high-to-low transition Propagation delay from falling edge of clock
Master/slave flip-flop Clock high-to-low transition Propagation delay from falling edge of clock
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Exercises

• page 425, 6.1-6.6, 6.9, 6.10, 6.12, 6.13, 6.14,
  6.17, 6.24, 6.25