Topic 11a: Asynchronous Logic Design II

1
Topic 11aAsynchronous Logic Design II

• SFSU ENGR 852
• Spring 2003
• 4/21

2
This Lecture

• Asynchronous Circuits
• Moore Mealy Standard Forms
• Design Example

3
Many Lectures Ago

• System design. Now design blocks.

4
When Asynchronous

• Clocked synchronous circuits
• Change of state only occurs in response to a
  clock pulse
• Input changes must happen away from clock pulse
• Conditions where this is too restrictive
• Inputs may change at any time
• Delay through wires are non-trivial
• We want faster results
• The power used to clock signals is unacceptable

5
Asynchronous Circuits

• Asynchronous circuits
• Operation is not synchronized by a clock
• State may change immediately when inputs change
• State flip-flops may change at slightly different
  times
• To simplify design here, well only consider
  fundamental mode asynchronous circuits
• The inputs can only change when circuit is in a
  stable condition (i.e. No internal signals are
  changing)
• All input signals are considered levels, rather
  than pulses or edges
• Inputs may not change simultaneously (only one
  input may change at a time)
• Asynchronous circuits may be structured as Mealy
  or Moore forms

6
Analysis Example Background

• Whats this do?
• Whats its problem?

7
Analysis Example Background

• Whats this do?
• How can you make this into a latch?

R
8
Analysis Example Background

• Whats this do?

9
D-Latch Analysis ExampleTables
We make a cut at Y/Y. Y is considered this
circuits state. Y is considered this circuits
next state.
10
D Latch Analysis ExampleTransition Table
Table for Y
11
Transition Table

• A transition table has one row for each possible
  combination of the state variables
• If the circuit has N feedback loops (N cut lines)
  the transition table has 2N rows
• The table has one column for each input
  combination
• A circuit with M inputs has 2M columns in its
  transition table
• The circuit continuously monitors its inputs

12
D Latch Analysis ExampleState Table
Table for State
Stable state
13
D-Latch Analysis ExampleOutput Table

• Q ClkD ClkY DY
• Q ClkD Y
• Y is the only internal state variable
• Combined state and output table (Entry
  NextState,QQ)

14
D-Latch Timing Diagram
15
Class Question 1(Table Analysis)
Clk D
State

• Which states are stable?
• Why?
• Draw a timing diagram to figure out what the
  function of this circuit is. Start at S0 with
  Clk1 and D1.

16
Where did the table come from?

• We found out what circuit the table on the
  previous slide described, but how can you derive
  the table?
• You can get it from analyzing a circuit as you
  did in the first example Except this ones more
  complicated

17
Positive Edge D Flip-Flop Analysis Example
18
Positive Edge D Flip-Flop Analysis Example
We make a cut at Y1/Y1, Y2/Y2, Y3/Y3. Y1, Y2,
Y3 are considered this circuits state. Y1,
Y2, Y3 are considered this circuits next
state.
19
Positive Edge D Flip-Flop Analysis Example
D
D
Q
20
Positive Edge D Flip-Flop Analysis Example
Y1
Y1
Clk
Y3
Y3
Q
Clk
Y2
Y2
D
Q
Rewrite circuit
21
Positive Edge D Flip-Flop Analysis Example
Y1
Y1
Clk
Y3
Y3
Q
Clk
Y2
Y2
D
Q
Find Equations
22
Transition Table for D Flip-Flop (Analysis
Example)
Fill in table
Y1Y2Y3
Y1Y2Y3
23
Transition Table for D Flip-Flop (Analysis
Example)
Fill in states
24
Transition Table for D Flip-Flop (Analysis
Example)
Circle stable states
25
Transition Table for D Flip-Flop (Analysis
Example)
Clk D
00 01 11 10 S0 S2,01
S2,01 S0,01 S0,01 S2 S2,01 S6,01 S6,01
S0,01 S3 S3,10 S7,10 S7,10 S0,01 S6 S2,01
S6,01 S7,11 S7,11 S7 S3,10 S7,10 S7,10
S7,10
State
Assuming circuit starts in a stable state, the
table can be simplified
26
Design Example 1

• An asynchronous network has two inputs and one
  output.
• The input sequence X1X200, 01, 11 causes the
  output Z to become 1.
• The next input change then causes the output to
  return to 0.
• No other input sequence will produce a 1 output.

X1 X2
Z
27
Asynchronous FSM Design Steps

• Construct a primitive flow table from the word
  statement of the problem
• Derive a minimum-row primitive flow table or
  reduced primitive flow table by eliminating
  redundant, stable total-states
• Convert the resulting table to Mealy form, if
  necessary, so that the output value is associated
  with the total state rather than the internal
  state
• Derive a minimum-row flow table, or merged flow
  table, by merging compatible rows of the reduced
  primitive flow table using a merger diagram.
  (Note The solution is not necessarily unique)
• Perform race-free, or critical race-free, state
  assignment, adding additional states if necessary
• Complete the output table to avoid momentary
  false outputs when switching between stable total
  states
• Draw logic diagram that shows ideal combinational
  next-state and output functions as well as
  necessary delay elements.

28
Design Example 1Step 1 Primitive Flow Table

• Problem description
• An asynchronous network has two inputs and one
  output.
• The input sequence X1X200, 01, 11 causes the
  output Z to become 1.
• The next input change then causes the output to
  return to 0.
• No other input sequence will produce a 1 output.
• Primitive flow table (First line plus
  transitions from first line)

X1X2
29
Design Example 1Step 1 Primitive Flow Table

• Primitive flow table (A few more lines)

X1X2
30
Design Example 1Step 1 Primitive Flow Table

• Primitive flow table (The final lines)
• Primitive flow table Only one stable state per
  row is allowed. Every change in input must cause
  an internal state change as well as a total state
  change.
• State 5 6 cannot lead to a 1 output without
  there being a reset first.

X1X2
31
Total State

• The total state of a circuit is the combination
  of the internal state (values stored in the
  feedback loops) and input state (the current
  input values)
• A stable total state is a combination of
  internal state and input state such that the
  present states (Example Y) equals the next
  state (Example Y)
• If the next state doesnt equal the present state
  then the total state is unstable

32
Design Example 1Step 1 Primitive Flow Table

• Primitive flow table (The final lines)
• Primitive flow table Only one stable state per
  row is allowed. Every change in input must cause
  an internal state change as well as a total state
  change.
• State 5 6 cannot lead to a 1 output without
  there being a reset first.

X1X2
33
Class Question 2(Design)

• A clock (Clk) and G (for gated) are the inputs to
  this circuit. An altered clock is the output Z.
• When G is high the output is the same as the
  input.
• When G is low the circuit outputs 0.
• All output clock pulses are complete. They are
  not cut-off even if G changes in the middle of a
  clock pulse.

34
Class Question 2(Design)

• Derive primitive flow table.

35
Class Question 2(Dont look unless you get stuck)

• Derivation of Primitive Flow Table

Clk G
00 01 11 10 Z
State 1 1 3 - 2 0
State 2 1 - 2 0
State 3 3 4 - 0
State 4 - 3 4 1
36
Class Question 2(Dont look unless you get stuck)

• Derivation of Primitive Flow Table

Clk G
00 01 11 10 Z
State 1 1 3 - 2 0
State 2 1 - 2 0
State 3 3 4 - 0
State 4 - 3 4 1
State 5 1 - - 5 1
State 6 - 3 6 - 0
37
Asynchronous FSM Design Steps

• Construct a primitive flow table from the word
  statement of the problem
• Derive a minimum-row primitive flow table or
  reduced primitive flow table by eliminating
  redundant, stable total-states
• Convert the resulting table to Mealy form, if
  necessary, so that the output value is associated
  with the total state rather than the internal
  state
• Derive a minimum-row flow table, or merged flow
  table, by merging compatible rows of the reduced
  primitive flow table using a merger diagram.
  (Note The solution is not necessarily unique)
• Perform race-free, or critical race-free, state
  assignment, adding additional states if necessary
• Complete the output table to avoid momentary
  false outputs when switching between stable total
  states
• Draw logic diagram that shows ideal combinational
  next-state and output functions as well as
  necessary delay elements.

38
Minimum-row primitive flow tableStep 2
Eliminate Redundant Rows

• Eliminate redundant stable total states
• Redundant states Two stable total states are
  equivalent if
• Their inputs are the same AND
• Their outputs are the same AND
• Their next-states are equivalent for each
  possible input

39
Step 2 Example(From Design example 1)

• Find rows with stable states in the same column
• 2 6
• 4 5
• Looking at 4 5
• Are their outputs the same?
• No. Therefore they are not
• equivalent states.
• Looking at 2 6
• Are their outputs the same?
• Yes. Might be equivalent.
• Are their next-states the same?
• The next-state for 00 input is the same.
• The next-state for 11 input is not the same.
• No. Therefore they are not equivalent states.

40
Step 2 Example(From Design example 2)

• Are there any equivalent states in the second
  example? (The gated clock)

41
Class Question 3(Removal of Redundant States)

• Remove redundant states

42
Class Question 3(Removal of Redundant States)

• Remove redundant states

43
Class Question 3(Removal of Redundant States)

• Table after redundant states removed.

44
Merger DiagramsStep 2 Eliminate Redundant Rows

• Merger Diagram Steps
• Tool for Finding Redundant States From Primitive
  Flow Table

45
Merger DiagramsStep 2 Eliminate Redundant Rows

• Steps
• Select Group of Possible Equivalent States
• States 1, 2, 6, 8 Might be Equivalent (Their
  Stable States are the Same)
• Draw Table

46
Merger DiagramsStep 2 Eliminate Redundant Rows

• Steps
• 3. Cross Off States With Different Outputs

47
Merger DiagramsStep 2 Eliminate Redundant Rows

• Steps
• 4. Write in Next States

48
Merger DiagramsStep 2 Eliminate Redundant Rows

• Steps
• Write Tables For ALL Possible Groups

49
Merger DiagramsStep 2 Eliminate Redundant Rows

• Steps
• Cross Out States That You KNOW are Not Equivalent

50
Merger DiagramsStep 2 Eliminate Redundant Rows

• Steps
• 6. Circle States That You KNOW ARE Equivalent

51
Merger DiagramsStep 2 Eliminate Redundant Rows

• Steps
• 6. Circle States That You KNOW ARE Equivalent

52
Merger DiagramsStep 2 Eliminate Redundant Rows

• Steps
• 6. Circle States That You KNOW ARE Equivalent

53
Merger DiagramsStep 2 Eliminate Redundant Rows

• Steps
• 6. Circle States That You KNOW ARE Equivalent

54
Merger DiagramsStep 2 Eliminate Redundant Rows

• Steps
• Repeat Steps 5 and 6 Until No More States Can Be
  Crossed Out or Circled
• Any States that are Left are Considered
  Equivalent

In this example, all state equivalence was
determined from information in the table. But
sometimes the Table Ends in a State Like the
Table to the Right
55
Merger DiagramsStep 2 Eliminate Redundant Rows

• Steps
• 8. Any States that are Left are Considered
  Equivalent

Here if CB then BD. Also if BD then CB.
This is a Circular Relationship. If There is No
Reason to Mark Them as Not Equivalent, Assume
They are Equivalent. Circular Relationships May
Have More than Two States.