week10-1

1

• Lecture 24
• Dynamic Logic
• Mar. 10, 2003

2
Topics

• Pseudo-nMOS gates.
• DCVS logic.
• Domino gates.

3
Pseudo-nMOS

• Uses a p-type as a resistive pullup, n-type
  network for pulldowns.

4
Characteristics

• Consumes static power.
• Has much smaller pullup network than static gate.
• Pulldown time is longer because pullup is
  fighting.

5
Output voltages

• Logic 1 output is always at VDD.
• Logic 0 output is above Vss.
• VOL 0.25 (VDD - VSS) is one plausible choice.

6
Producing output voltages

• For logic 0 output, pullup and pulldown form a
  voltage divider.
• Must choose n, p transistor sizes to create
  effective resistances of the required ratio.
• Effective resistance of pulldown network must be
  comptued in worst caseseries n-types means
  larger transistors.

7
Transistor ratio calculation

• In steady state logic 0 output
• pullup is in linear region,Vds Vout - (VDD -
  VSS)
• pulldown is in saturation.
• Pullup and pulldown have same current flowing
  through them.

8
Transistor ratio, contd.

• Equate two currents
• Idp Idd.
• Using 0.5 mm parameters, 3.3V power supply
• Wp/Lp / Wn/Ln 3.9.

9
DCVS logic

• DCVSL differential cascode voltage logic.
• Static logicconsumes no dynamic power.
• Uses latch to compute output quickly.
• Requires true/complement inputs, produces
  true/complement outputs.

10
DCVS structure
11
DCVS operation

• Exactly one of true/complement pulldown networks
  will complete a path to the power supply.
• Pulldown network will lower output voltage,
  turning on other p-type, which also turns off
  p-type for node which is going down.

12
DCVS example
13
Precharged logic

• Precharged logic uses stored charge to help
  evaluation.
• Precharge node, selectively discharge it.
• Take advantage of higher speed of n-types.
• Requires multiple phases for evaluation.

14
Domino logic

• Uses precharge clock to compute output in two
  phases
• precharge
• evaluate.
• Is not a complete logic familycannot invert.

15
Domino gate structure
16
Domino phases

• Controlled by clock ?.
• Precharge p-type pullup precharges the storage
  node inverter ensures that output goes low.
• Evaluate storage node may be pulled down, so
  output goes up.

17
Domino buffer

• Output inverter is needed for two reasons
• make sure that outputs start low, go high so that
  domino output can be connected to another domino
  gate
• protects storage node from outside influence.

18
Domino operation
19
Domino effect

• Gate outputs fall in sequence

gate 1
gate 2
gate 3
20
Monotonicity

• Domino gates inputs must be monotonically
  increasing glitch causes storage node to
  discharge.

21
Output buffer

• Inverting buffer isolates storage node. Storage
  node and inverter have correlated values.

22
Using domino logic

• Can rewrite logic expression using De Morgans
  Laws
• (a b) ab
• (ab) a b
• Add inverters to network inputs/outputs as
  required.

23
Domino and stored charge

• Charge can be stored in source/drain connections
  between pulldowns.
• Stored charge can be sufficient to affect
  precharge node.
• Can be averted by precharging the internal
  pulldown network nodes along with the precharge
  node.

24
Example 1
25

• Lecture 25
• RC Transmission Line
• Mar. 12, 2003

26
Topics

• Wire delay.
• Buffer insertion.
• Crosstalk.
• Inductive interconnect.

27
Wire delay

• Wires have parasitic resistance, capacitance.
• Parasitics start to dominate in deep-submicron
  wires.
• Distributed RC introduces time of flight along
  wire into gate-to-gate delay.

28
RC transmission line

• Assumes that dominant capacitive coupling is to
  ground, inductance can be ignored.
• Elemental values are ri, ci.

29
RC trees

• Generalization of RC transmission line.

30
RC crosstalk

• Crosstalk slows down signals---increases settling
  noise.
• Two nets in analysis
• aggressor net causes interference
• victim net is interfered with.

31
Crosstalk delay

• There is an optimum wire width for any given wire
  spacing---at bottom of U curve.
• Optimium width increases as spacing between wires
  increases.

32
Example 2
33

• Lecture 26
• Sequencial Logic
• Mar. 14, 2003

34
Topics

• Memory elements.
• Basics of sequential machines.

35
Memory elements

• Stores a value as controlled by clock.
• May have load signal, etc.
• In CMOS, memory is created by
• capacitance (dynamic)
• feedback (static).

36
Variations in memory elements

• Form of required clock signal.
• How behavior of data input around clock affects
  the stored value.
• When the stored value is presented to the output.
• Whether there is ever a combinational path from
  input to output.

37
Memory element terminology

• Latch transparent when internal memory is being
  set from input.
• Flip-flop not transparentreading input and
  changing output are separate events.

38
Clock terminology

• Clock edge rising or falling transition.
• Duty cycle fraction of clock period for which
  clock is active (e.g., for active-low clock,
  fraction of time clock is 0).

39
Memory element parameters

• Setup time time before clock during which data
  input must be stable.
• Hold time time after clock event for which data
  input must remain stable.

clock
data
40
Dynamic latch

• Stores charge on inverter gate capacitance

41
Latch characteristics

• Uses complementary transmission gate to ensure
  that storage node is always strongly driven.
• Latch is transparent when transmission gate is
  closed.
• Storage capacitance comes primarily from inverter
  gate capacitance.

42
Latch operation

• ? 0 transmission gate is off, inverter output
  is determined by storage node.
• ? 1 transmission gate is on, inverter output
  follows D input.
• Setup and hold times determined by transmission
  gatemust ensure that value stored on
  transmission gate is solid.

43
Stored charge leakage

• Stored charge leaks away due to reverse-bias
  leakage current.
• Stored value is good for about 1 ms.
• Value must be rewritten to be valid.
• If not loaded every cycle, must ensure that latch
  is loaded often enough to keep data valid.

44
Stick diagram
VDD
Q
D
VSS
?
?
45
Layout
VDD
D
Q
VSS
?
?
46
Multiplexer dynamic latch
47
Non-dynamic latches

• Must use feedback to restore value.
• Some latches are static on one phase
  (pseudo-static)load on one phase, activate
  feedback on other phase.

48
Flip-flops

• Not transparentuse multiple storage elements to
  isolate output from input.
• Major varieties
• master-slave
• edge-triggered.

49
Master-slave flip-flop
master
slave
D
Q
?
50
Master-slave operation

• ? 0 master latch is disabled slave latch is
  enabled, but master latch output is stable, so
  output does not change.
• ? 1 master latch is enabled, loading value
  from input slave latch is disabled, maintaining
  old output value.

51
Sequential machines

• Use memory elements to make primary output values
  depend on state primary inputs.
• Varieties
• Mealyoutputs function of present state, inputs
• Mooreoutputs depend only on state.

52
Sequential machine definition

• Machine computes next state N, primary outputs O
  from current state S, primary inputs I.
• Next-state function
• N ?(I,S).
• Output function (Mealy)
• O ?(I,S).

53
FSM structure
54
Constraints on structure

• No combinational cycles.
• All components must have bounded delay.

55
Signal skew

• Machine data signals must obey setup and hold
  timesavoid signal skew.

56
Clock skew

• Clock must arrive at all memory elements in time
  to load data.

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