JTAG

1
JTAG

• Ref http//en.wikipedia.org/wiki/Joint_Test_Actio
  n_Group
• JTAG Standard Test Access Port and Boundary-Scan
  Architecture
• Joint Test Action Group (JTAG) was formed in 1985
  in response to the advent of multilayered PCBs
  and surface-mount technology, which precluded the
  use of traditional probes
• JTAG became an international standard, IEEE
  1141.9-1990, in 1990
• Boundary scan is a testing method for monitoring
  PCB trace integrity, pin signal state, IC
  components, and debuggin embedded systems.
• Boundary scan used test cells, like circuits,
  located at strategic positions on the PCB to
  perform tests. For instance, two cells might be
  located at opposite ends of a trace. By sending a
  signal from one cell to the next the trace
  integrity can be determined.
• JTAG added BSDL (Boundary Scan Description
  Language) in 1994 as a means to standardize the
  scanning process. Example http//www.maxim-ic.com
  /tools/bsdl/
• In embedded systems development the JTAG
  interface provides a means by which developers
  can access a debugging module within the CPU,
  which can be accessed and controlled by use of an
  ICE (In-Circuit Emulator) debug tool.
• JTAG access a CPUs scan chain (collection of
  internal registers) to analyze its state and
  detect potential faults
• JTAG-enabled chips have a 5/4-pin connection
  (optional test rest pin), which can daisy-chained
  with other ships to provide a single diagnostic
  path
• Pins are Data In, Data Out, Clock, and Test Mode
  Select (puts chip in specific state)
• Test instructions are clocked in serially and
  result data clocked out.
• Typical operational speed 10 100MHz

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• http//www.urjtag.org/
• http//openocd.berlios.de/web/
• http//www.freescale.com/files/dsp/doc/app_note/AN
  2074.pdf
• http//www.freescale.com/files/product/doc/AN1935.
  pdf?WT_TYPEApplicationNotesWT_VENDORFREESCALE
  WT_FILE_FORMATpdfWT_ASSETDocumentation