The ARM7TDMI Processor

1
The ARM7TDMI Processor

• Block Diagram
• Vector Table
• Exception Priorities and Interrupts
• JTAG Interface

2
The ARM7TDMI
Clock Control
Configuration
Clock Control
Interrupts
Initialization
Configuration
Bus Control
Interrupts
Initialization
Debug
Boundary Scan Extensions
Coprocessor Interface
JTAG Controls
Power
3
The ARM Vector table
The ARM Vector Table
0xFFFF FFFF
32-bit Memory Space
Address Vector
0x0000 0000 RESET
0x0000 0004 Undefined Instruction
0x0000 0008 SWI Software Interrupt
0x0000 000C Abort (Prefetch) Bus Error Inst Fetch
0x0000 0010 Abort (Data) Bus Error Data Fetch
0x0000 0014 Reserved (not used)
0x0000 0018 IRQ Interrupt
0x0000 001C FIQ Interrupt
0x0000 0000
4
Exception Priorities

• Highest Priority
• Reset
• Data Abort
• FIQ
• IRQ
• Prefetch Abort
• Undefined, SWI
• Lowest Priority

• NOTES
• Data Abort, Prefetch Abort, and Undefined
  Represent Unexpected and Erroneous Software
  Operation.
• IRQ is most common exception during run-time.

5
IRQ and FIQ Interrupts
Gen Module
ARM7TDMI Core
IRQ
FIQ
BBus
NetARM ASIC

• NOTES
• There is no direct external access to either IRQ
  of FIQ.
• FIQ can occur while FIRQ is being processed.

6
JTAG Debugger Interface
ARM7TDMI Core
TRST
TCK
TMS
TDI
TDO
BBus
NetARM ASIC