ARM Processor

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ARM Processor

• www.clabsys.com

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Agenda

• ARM Core Data Flow Model
• Registers
• Program Status Register
• Pipeline
• Exceptions
• Core Extensions
• ARM Architecture Revision

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ARM Core Data Flow Model
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Registers

• ARM has 37 registers which are 32-bits long
• Program counter 1
• CPSR 1
• SPSR 5
• General purpose registers 30
• The current processor mode governs which of
  several banks is accessible

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ARM Register Set
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Program Status Register (PSR)

• CPSR holds the current status information
• SPSR preserves the CPSR during exceptions

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PSR Condition Flags

• N Negative result from ALU
• Z Zero result from ALU
• C ALU operation Carried out
• V ALU operation overflowed
• Q Overflow Saturation
• ARMv5TEJ only

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PSR Processor States
ARM Thumb Jazelle
Instruction Size 32-bit 16-bit 8-bit
Core instructions 58 30 Over 60 of Java H/W The rest S/W
cpsr T0 J0 T1 J0 T0, J1
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PSR Interrupt Masks

• used to stop specific interrupt requests from
  interrupting the processor
• I 1
• Disables the IRQ
• F 1
• Disables the FIQ

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PSR Processor Mode
Mode Abbreviation Privileged Bits 40
Abort abt Yes 10111
Fast Interrupt fiq Yes 10001
Interrupt request irq Yes 10010
Supervisor svc Yes 10011
System sys Yes 11111
Undefined und Yes 11011
User usr No 10000
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Pipeline

• The mechanism a RISC processor uses to execute
  instructions

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Exceptions

• Reset
• When power is applied
• Undefined instruction
• When the processor cannot decode an instruction
• Software interrupt
• When the processor meet an SWI instruction

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Exceptions (Cont.)

• Prefetch abort
• When the processor attempts to fetch an
  instruction from an address without the correct
  access permission
• Data abort
• When an instruction attempts to access data
  memory without the correct access permissions

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Exceptions (Cont.)

• Interrupt request (IRQ)
• When an external hardware interrupts the normal
  execution flow of the processor
• Fast interrupt request (FIQ)
• When an hardware requiring faster response times
  interrupts the normal execution flow of the
  processor

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Exception vector table
Exception Shorthand Vector address High address
Reset RESET 0x00000000 0xffff0000
Undefined instruction UNDEF 0x00000004 0xffff0004
Software interrupt SWI 0x00000008 0xffff0008
Prefetch abort PABT 0x0000000c 0xffff000c
Data abort DABT 0x00000010 0xffff0010
Reserved - 0x00000014 0xffff0014
Interrupt request IRQ 0x00000018 0xffff0018
Fast interrupt request FIQ 0x0000001c 0xffff001c
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Exception handling

• When an exception occurs,
• Copies CPSR into SPSR_ltmodegt
• Sets appropriate CPSR bits
• Change to ARM state
• Change to exception mode
• Disable interrupts (if appropriate)
• Stores the return address in LR_ltmodegt
• Set PC to vector address

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Exception handling (Cont.)

• To return,
• Restore CPSR from SPSR_ltmodegt
• Restore PC from LR_ltmodegt

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Core Extensions

• Cache
• TCM (Tight Coupled Memory)
• Memory Management Hardware
• Non-protected Memory
• MPU (Memory Protection Unit)
• MMU (Memory Management Unit)
• Coprocessors

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Cache

• Improves the overall system performance

lt A simplified Von-Neumann architecture with
cache gt
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TCM

• Improves deterministic real-time response

lt A simplified Harvard architecture with TCMs gt
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Memory Management Hardware

• Non-protected memory
• Small embedded systems that require no protection
  from rouge application
• MPU
• Simple systems that uses a limited number of
  memory regions
• MMU
• More sophisticated platform operating systems
  that support multitasking

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Coprocessors

• Extends the processing features of a core by
  extending the instruction set or by providing
  configuration registers
• Vector Floating-Point (VFP) operations
• CP10/CP11
• System Control Coprocessor
• CP15
• Controls the cache, TCMs, MPU, MMU

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ARM Architecture Revision

• ARM xyzTDMIEJF-S
• ARM7/ARM9/ARM10/ARM11
• ARM7TDMI/ARM720T/ARM7EJ-S
• ARM920T/ARM922T/ARM940T
• ARM926EJ-S/ARM946E-S/ARM966E-S
• ARM1020E/ARM1020E/ARM1022E
• ARM1136J-S/ARM1136JF-S

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ARM7

• Von Neumann architecture
• Unified cache
• Both data and instructions use the same bus
• 3-stage pipeline
• ARMv4T
• Example
• ARM7TDMI
• ARM720T
• ARM7EJ-S

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ARM7 (Cont.)
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ARM9

• Harvard architecture
• Saperated Instruction memory interface
• Data memory interface
• 5 stage pipeline
• Example
• ARM920T/ARM922T
• ARM940T
• ARM946E-S/ARM966E-S
• ARM920EJ-S

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ARM9 (Cont.)
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ARM10

• 6 stage pipeline
• Vector Floating-Point
• Example
• ARM1020E
• Separate 32K DI caches
• VFP/MMU
• Dual 64-bit bus interface
• ARM1026EJ-S
• Both MPU and MMU

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ARM11

• 8-stage pipeline
• ARMv6
• SIMD (Single Instruction Multiple Data)
• Example
• ARM1136J-S
• ARM1136JF-S

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StrongARM/Xscale

• Harvard architecture
• separate DI caches
• 5-stage pipeline
• Not support the Thumb instruction set