AT91 Interrupt Handling

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AT91 Interrupt Handling
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What are interrupts ?

• Stops the execution of main software
• Redirects the program flow, based on an event, to
  execute a different software subroutine
• Interrupt behaviour

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Interrupt sources (1/2)

• External Interrupts
• Allows an external event to stop program
  execution
• Can alert the core by an edge transition or a
  level
• Signal can originate from external peripherals or
  systems
• Example external switch closure Interrupts

AT91
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Interrupt sources (2/2)

• Internal Interrupts
• Originate from on-chip peripherals
• Notifies core that peripheral needs servicing
• Typically can occur at any time
• Can originate from software

Counter overflow
Timer/Counter
End of conversion
ADC
End of transmission
USART
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ARM7TDMI Interrupt Sources

• Two physically independent sources
• Fast interrupt FIQ
• Used for fast interrupt handling
• Private registers
• Enable/disable with F bit in CPSR
• Last vector in the exception vector table
• Interrupt IRQ
• Standard interrupt request
• Enable/disable with I bit in CPSR

ARM7TDMI Processor
IRQ
FIQ
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Advanced Interrupt Controller (1/3)

• Features
• 8-level Priority
• Up to 32 Interrupt sources
• Individually maskable
• Hardware interrupt vectoring
• Internal Interrupt sources
• Level sensitive or edge triggered
• External Interrupt sources
• Low/High level sensitive or positive/negative
  edge triggered

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Advanced Interrupt Controller (2/3)

• Block Diagram

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Advanced Interrupt Controller (3/3)
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Atomic Interrupt Control (1/2)

• For multi-task systems, it is sometimes useful to
  share peripherals
• Interrupt Mask update is interruptible
• Mask Register may be lost

OS Scheduler
Task 2
Task 1
Read IMR
Task 1
Task 2
Read IMR
Modify
Modify
Peripheral
Write IMR
Write IMR
OS Scheduler
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Atomic Interrupt Control (2/2)

• Basic solution is to mask interrupt at core level
  before modifying IMR
• ARM7TDMI limitations
• The CPSR is accessible only in ARM state and can
  be updated only from Privileged Mode
• Usual solution is to switch in Supervisor Mode
  with a SWI
• AT91 microcontrollers solution
• Enabling or disabling an interrupt request in
  only one instruction
• STR rx,ry,IER
• STR rx,ry,IDR

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Interrupt Vectors

• Each interrupt source is associated with a Source
  Vector Register (AIC_SVR0-AIC_SVR31) which
  contains the address of the interrupt handler
• When the Interrupt Vector Register (AIC_IVR) is
  read, it automatically returns the contents of
  the source vector register corresponding to the
  active interrupt

AIC Source vectors
AIC Interrupt vectors
ARM Exception vectors
AIC_SVR31
0xFFFFF0FC
ldr
pc,pc,-F20
AIC_SVR30
0x0000001C
FIQ
AIC_FVR
0xFFFFF104
IRQ
0x00000018
AIC_IVR
0xFFFFF100
Index
ABORT (Data)
Interrupt Id.
ABORT (Fetch)
SWI
UNDEF
RESET
AIC_SVR1
AIC_SVR0
0xFFFFF080
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Interrupt Prioritization (1/4)

• The NIRQ line is controlled by an 8-level
  priority encoder
• Each source has a programmable priority level of
  7 to 0. Level 7 is the highest priority.
• The AIC manages the prioritization by using an
  internal stack on which the current interrupt
  level is automatically pushed when AIC_IVR is
  read, and popped when AIC_EOICR is written
• Between these two events, the software can manage
  the state and the mode of the core in order to
  re-enable the IRQ line and to allow an interrupt
  with a higher priority.

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Interrupt Prioritization (2/4)

• When an interrupt is managed by the processor,
  R14_irq and SPSR_irq are automatically
  overwritten without being saved
• It is mandatory to save these registers before
  re-enabling the IRQ line and to restore them
  before exiting the interrupt routine
• If the interrupt treatment performs function
  calls (Branch with link), R14_irq is used. In
  this case, IRQ can not be re-enabled while the
  processor is in IRQ mode
• It is mandatory to first change the processor
  mode to SYSTEM mode in order to keep all
  exceptions available

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Interrupt Prioritization (3/4)

• The standard sequence of an interrupt handler is
• Validate the nested interrupts
• Save R14_irq and SPSR_irq in the IRQ stack
• Set the mode bits in CPSR with the SYSTEM Mode
  value
• Re-enable IRQ by clearing bit I in CPSR
• Perfom interrupt treatment
• call C handler
• Disable the nested interrupts
• Disable IRQ by clearing bit I in CPSR
• Set the mode bits in CPSR with the IRQ Mode value
• Restore R14_irq and SPSR_irq from the IRQ stack
• This sequence is automatically preceded by a read
  of AIC_IVR and must be followed by a write in
  AIC_EOICR before exiting from the interrupt

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Interrupt Prioritization (4/4)
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Spurious Interrupt (1/2)

• A Spurious Interrupt occurs when the ARM7TDMI
  processor is interrupted and the source of
  interrupt has disappeared when IVR is read
• With any sources programmed to be level
  sensitive, if the interrupt signal of the AIC
  input is de-asserted at the same time as it is
  taken into account by the ARM7TDMI.
• If an interrupt is asserted at the same time as
  the software is disabling the corresponding
  source through AIC_IDCR.

Operation
STR xxx_IDR
xxx
xxx
(0x018) Branch to routine
NIRQ
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Spurious Interrupt (2/2)

• The AIC is able to detect these Spurious
  Interrupts and returns the Spurious Vector when
  the IVR is read
• The Spurious Vector can be programmed by the user
  when the vector table is initialized.
• It is mandatory for the Spurious Interrupt
  Service Routine to acknowledge the Spurious
  behavior by writing to the AIC_EOICR (End of
  Interrupt) before returning to the interrupted
  software.
• Spurious Interrupt Service Routine Sequence
• Adjust and save lr_irq in stack
• Write the End of Interrupt Command Register
• Run a trace function if necessary
• Returns by restoring LR directly in PC

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AT91 Interrupt Control Strengths (1/2)

• Atomic Interrupt Enable/Disable
• Interrupt Controller Level
• Peripheral Level
• Resolve the problem of RISC
• No Read/Modify/Write Instruction
• Limit the Spurious Exceptions
• Fully Secured
• Spurious Interrupt Protection
• Spurious Vector Register
• Debugger Protection
• Protect Mode avoids the debugger to start an
  interrupt
• Automatic Vectoring
• Speeds up the interrupt handler branching

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AT91 Interrupt Control Strengths (2/2)

• Highly Programmable Sources
• External Sources
• Edge/Level Selection
• Internal Sources
• Edge/Level Selection
• Built In Test Support
• Force any Interrupt Assertion
• High Level Operating System Compatible
• Source Status Register gives the current source
  number
• Pending Interrupt Register
• NIRQ, NFIQ Signals Mirror