Loai Tawalbeh Lecture

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Loai Tawalbeh Lecture 3
Digital Logic Review

• Flip-Flops, Registers, Shift registers, Counters,
  Memory

3/3/2005
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Flip-Flops

• A storage element employed in clocked
  sequential circuits.
• It is a binary cell Capable of storing one bit
  of information.
• One Flip-Flop for each bit.
• Characteristic Tables shows the behavior of the
  F-Fs (sec 1.6)
• F-Fs analysis given logic Diagram, find the
  state diagram.
• F-Fs design given the state diagram, find the
  logic diagram.
• Examples in section 1.7

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Notation, characteristic equations

• Q means the next value of Q. (or Q)
• Excitation is the input applied to a device
  that determines the next state.
• Characteristic equation specifies the next
  state of a memory device as a function of its
  excitation.
• S-R latch Q S R Q
• Edge-triggered D flip-flop Q D
• When does Q becomes Q

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Example state machine
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Excitation equations
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Excitation Functions- Table 1-3, page 27
S Q
D
Q
D-FF
c
Clk
Q'
R Q
J Q
T
Q
Clk
D-FF
K Q'
Clk
Q'
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The Design Procedure

• Obtain a binary description of the system.
• Select the type of flip-flops.
• Determine the inputs to the flip-flops (use the
  excitation function).
• Design a combinational network for the FF input
  functions Next State.
• Design a combinational network for the system
  output.
• Example in the class

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Registers

• Storage Element accessed faster than the memory

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4-bit Register
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Shift Register
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Shift Register Control
s(t) 0101

• z(t) s(t)
• Output has the same value as the current state

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4-bit Bi-directional Shift Register
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Counters
A2
A0
A1
A3
Q
Q
Q
Q
J K
J K
J K
J K
Clock Counter Enable (CE)
Output Carry
JK FF Characteristic Table
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MEMORY COMPONENTS
0
Logical Organization
words
(byte, or n bytes)
N - 1
Random Access Memory (RAM) - Each word
has a unique address - Access to a word
requires the same time independent of
the location of the word - Organization
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Read-Only Memories
K- address lines

• Program storage
• Boot ROM for personal computers
• Complete application storage for embedded systems.

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Example
Design a 32K-8 bit ROM using blocks of a 4k-8 bit
Roms. Solution
1- How many address lines are needed? 32k
25X210215 So, 15 address lines needed to map
32k locations in the ROM.
2- How many 4k ROM blocks are needed? 32k/4k 8
blocks
3- How many address lines are needed for each 4k
ROM block? 4k22X210 212, so 12 address
lines.
So we connect the MS 12 address lines to each one
of the 8 (4k-blocks) The remaining 3 LS address
lines are inserted to a 3-8 decoder to choose the
appropriate 4k ROM block.
Draw the circuit.