Synchronous FullScan for Asynchronous Handshake Circuits

1
Synchronous Full-Scan for Asynchronous Handshake
Circuits

• Frank te Beest
• Ad Peeters Kees van Berkel Hans
  Kerkhoff
• University of Twente / MESA Research Institute
• Philips Research Laboratories

2
Outline

• Asynchronous Handshake Circuits
• Test Challenges
• Full Scan Testing
• L1L2 Scan Optimization
• Conclusion

3
Asynchronous circuits

• Synchronous clock
• Asynchronous handshake

data
clk
req
req
ack
control block
ack
data
data path
4
Asynchronous benefits

• Low Power
• Low Noise and Electro Magnetic Emission
• Modularity
• Robustness towards Power, Temperature and
  Process variations
• ( in USA Higher operating speed)

5
Tangram Design Method

• High level behavioral specification (while, do,
  if, case)
• 2-step synthesis scheme
• Compilation into handshake circuit
• Mapping onto gate-level netlist
• Resulting circuits
• 4-phase handshake in control block
• Conventional data path

Tangram program
Handshake circuit
Gate-level netlist
compilation
mapping
6
Asynchronous circuits

• Any asynchronous circuit can be partitioned in
  combinational logic and feedback loops
• This partitioning is not unique!

7
Test challenge

• No Global clock
• Combinational loops
• ( possible Redundant logic )
• ( possible Synchronization / Arbitration )
• Tester restrictions
• e.g. single free-running clock
• Cost restrictions
• Test time
• Silicon area

8
Design rules and test approach

• Break loops with scan and apply existing test
  tools
• Traditional scan rules
• Use only synchronous (clocked) feedback
• Use only flip-flops as storage elements
• Avoid redundant gates
• Avoid gated clocks
• Clocks may not feed data-inputs of flip-flops
• In asynchronous designs none of these rules is
  satisfied

9
Cutting feedback loops

• Inserting an transparent flip-flop in each
  feedback loop enables a synchronous, an
  asynchronous, and a scan mode of operation

Combinational logic
M
S
10
Source of loops

• C-elements asynchronous state-holding elements

b
z
a
Asymmetrical C-element
b
z
Symmetrical C-element
a
11
Scan C-elements
Custom cell implementation
Decomposition in standard cells
a
b
ti
b
a
b
?1
z
ti
z
?1
z
a
?1
?1
?1
?2
z
?2
b
a
ti
a
b
enable and multiplex logic
original C-element
slave latch
12
Tangram circuit structure
Control block
WriteReq
Start
Logic gates
C
C
C
WriteAck
Parameters
Conditions
Enable
...
D
D
Inputs
Combinational
Logic
L1
...
Outputs
Latch
Flip-flop
Data path
13
Test Conflict
Clock signals
Data signals
Control block
Tm
WriteReq
Start
Clk1
Logic gates
Clk1
Clk2
Se
...
...
Sin
C
C
C
data and clock signals conflicting
Sout
WriteAck
Parameters
Conditions
Enable
...
Sin
...
D
D
D
Inputs
Combinational
Sout
Logic
L1
L2
...
Outputs
Clk2
Latch
Flip-flop
Data path
14
Test generation

• Use remodeling for C-elements and latches
• Separate test generation for control and data
  path
• Scan insertion and remodeling implemented in new
  tool, compatible to existing test tools
• ATPG with existing test pattern generation tool
• Merge into top-level test with test protocol
  expansion tool

15
Full Scan Results

• Fully automated structural test method for
  asynchronous circuits
• gt 99 fault coverage
• No redundant circuitry
• ATPG on remodeled circuit is valid for real
  circuit
• Benefits from flexibility and further development
  of existing tools

16
Full Scan (Standard cell implementation)
17
Full Scan (Custom cell implementation)
18
Separate controllability and observability
Combinational logic 1
1
1
2
2
Combinational logic 2
19
L1L2 remodeling for ATPG
Sin
Sout
D
1
2
Se1
L1
Clk1
20
L1L2 remodeling for ATPG
Sin
Sout
D
D
1
1
L2
Se1
L1
Clk1
Clk2
21
L1L2 Scan (Data path only)
22
Further improvements

• L1L2 in control block
• More dedicated library cells
• Better algorithms
• Partial scan
• Requires sequential ATPG
• Can build upon full scan results
• High-level design strategy
• Design for testability rules for VLSI designers

23
Roadmap
24
Conclusion

• Any asynchronous circuit can be transformed into
  a scan testable circuit
• The scan circuits thus obtained are essentially
  asynchronous circuits with a synchronous mode(or
  synchronous with an asynchronous mode)
• These circuits are fully controllable and
  observable
• Test coverage of gt99 stuck-at has been achieved
• Area cost projected to go down to 20
• First IC in development