RISC vs. CISC

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RISC vs. CISC
By Frank Norris
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Topics of Discussion

• Technological limitations which lead up to the
  design philosophies of RISC and CISC
• RISC and CISC Processor Methodologies
• Processing Comparisons
• Todays Processors Combining RISC and CISC for
  better performance

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Technological Limitations leading to CISC design
philosophy

• In the 1970s 80s memory was both slow and
  expensive.
• High cost and poor performance facilitated the
  need for compact and efficient code. (Assembly
  Language for direct execution)
• Code written in a high level language took much
  longer to translate into assembler, which lead to
  bloated code and slower program execution.
• The CISC philosophy was to shift some of the
  programming burden to the hardware level.

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CISC and Performance

• time/program (instructions/program) x
  (cycles/instruction) x (time/cycle)
• CISC seeks to reduce the number of instructions
  executed to perform a task thereby increasing
  overall performance

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CISC Methodology Use additional hardware to
perform code translation and optimization.

• Complex instructions written in a high level
  language translate directly into exactly one
  instruction in assembler.
• Reduced difficulty in writing compilers, improve
  code compaction, and ease debugging.
• Improve the efficiency of programs written in
  high level languages.
• Reduce software development costs as well as the
  size and complexity of programs/systems.

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Complex Instructions
To multiply two numbers, first load each operand
from a location in main memory (locations 11
through 64) into one of the six registers (A, B,
C, D, E, or F). Once loaded, they can be
multiplied by the execution unit (or
ALU). 1. LOAD A, 23 2. LOAD B, 52
3. MULT A, B 4. STORE 23, A
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Complex Instructions

• CISC rolls up this instruction set into one
  compact instruction to be handled by the decoder.
• MULT 23, 52
• Microcode engine within the CPU decodes the
  complex instructions and executes microcode
  programs to carry out the task

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Pros and Cons of CISC

• Pro
• Complex instructions operate directly on main
  memory.
• Programmer is no longer required to do a direct
  call to LOAD and STORE operations as they are now
  handled by hardware.
• Compiler has less work to translate statements in
  a high level language to assembly language.

• Con
• Microcode became more difficult to test and debug
  as systems became more complex requiring numerous
  patches to fix bugs.
• Programmers werent using the more complex
  instructions sets in favor of smaller
  instructions that accomplished the same result.
• The use of memory operands caused structural
  hazards preventing concurrent execution of
  instructions. (pipelining)

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Observations leading to RISC methodology

• Only 20 of the available instructions are being
  used. Transistors currently allocated to these
  complex instruction sets could be better utilized
  elsewhere to gain performance.

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RISC Methodology Simple instructions and the
return of direct execution

• Reestablish the direct execution model since most
  complex instructions were not utilized.
• Do away with the microcode engine (eliminate the
  overhead involved in decoding)
• Reduce the instruction set by eliminating all but
  the most necessary instructions
• Replace the complex instructions with groups of
  smaller ones

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RISC and Performance

• time/program (instructions/program) x
  (cycles/instruction) x (time/cycle)
• RISC seeks to reduce the number of CPU cycles per
  instruction executed to increase overall
  performance

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RISC and Performance

• RISC instructions, wherever possible, should only
  take one instruction cycle to complete.
• Pipelining is only really feasible where
  instructions of varying degrees of complexity are
  not dealt with, which yields a lower number of
  average cycles per instruction, thereby
  increasing performance.

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Advantages of RISC

• RISC uses only register to register operations
• Only LOAD and STORE operations have access to
  memory
• Separation of LOAD and STORE instructions allows
  the compiler to shift these operations around for
  maximum efficiency during execution.
• Simple instructions require fewer transistors
  which make the chips easier to design and cheaper
  to produce

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Todays Processors

• Most CPUs today are based on the CISC
  methodology, but with the increase in transistor
  resources the RISC methodology is also in use
  within the same processor.(Intel, AMD, etc.)
  All modern processors utilize the following
  advancements
• on-chip cache clocked as fast as the processor
• additional functional units for superscalar
  execution
• support for floating point operations
• branch prediction
• out-of-order execution
• While keeping backward compatibility with older
  x86 standards and utilizing a RISC processing
  core increases overhead, market factors have
  dictated that this be the case for manufacturers.

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Todays Processors

• Intels newest processors blur the barrier
  between RISC and CISC even more through the
  following advancements
• Rapid Execution Engine
• Two Arithmetic Logic Units allowing basic integer
  instructions to execute in 1/2 a clock cycle.
• Execution Trace Cache
• Stores 12K decoded microcode operations in the
  order of program execution. This removes the
  decoder from the main execution loop and improves
  cache efficiency.
• Data Prefetch Logic
• Anticipates data needed by an application and
  pre-loads it into the Advanced Transfer Cache.
• Streaming SIMD Extensions 2 (SSE2) Instructions
• Special instruction set to accelerate video,
  speech, image processing, encryption, and
  science/engineering applications.
• Hyper-Threading Technology
• two logical processors that can execute
  different tasks simultaneously using shared
  hardware resources.

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Summary

• CISC processors are more expensive to build, and
  maintaining the microcode for these processors
  becomes increasingly more complex.
• RISC processors gain a performance advantage
  through the elimination of microcode, pipelining
  and caching, and the use of a direct execution
  control unit.
• Technological advancements have blurred the
  boundary between true RISC and CISC architectures
  in recent years, and this trend continues today.
  Designers are actively looking for things to
  integrate into the chips to make use of the
  increased transistor resources and make
  performance improvements.

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Sources

• http//cpusite.examedia.n1/docs/cisc_vs_risc.html
• http//amiga.emugaming.com/riscisc.html
• http//www.heyrick.co.uk/assembler/riscvcisc.html
• http//www.arstechnica.com/cpu/4q99/risc-cisc/rvc-
  1.html
• http//developer.intel.com/design/Pentium4/prodbre
  f/netburst