Exam

1
Exam

• General Comments
• Provisional date/time/venue 16/05/2005, 9am,
  C1058-1060(make sure to re-check at
  http//www.timetable.ul.ie/ !)
• Duration 2½ h

2
ED5532 Instructions
3
ET4508 Instructions
4
General recommendations

• Recommendations for exam preparation
• Go through slides (on the web)
• Use lecture notes as the reference material
• Look at past exam papers (in particular
  2003-2004)
• Selected exercises taken from tutorial sheets 1-3

5
Focus Part A

• Focus of Part A Multiple choice
• MPU fundamentals
• Buses, address decoding, read and write cycles,
  memory-mapped I/O vs separate I/O mapping,
  stacks, interrupts, DMA, etc
• Processors 8086 (main features, register set,
  functional units, bus interface, minimum system)
• Processor evolution (86, 286, 386, 486, Pentium,
  MMX, P6, P7), main features, register sets, bus
  widths, bus interface, burst mode
• Modes of operation (real mode vs protected mode)
  main differences
• Instruction queues, instruction pipelines,
  super-scalar architecture, RISC vs CISC
• Memory devices (static/dynamic RAM, ROM, EPROM,
  Flash), width of data bus and address bus,
• ISA, EISA, VESA, main features
• PCI bus, main features
• AGP bus, main features

6
Focus Part B

• Processors RISC vs CISC
• Cache memories
• Pipelines
• Memory management (segmentation and paging)
• look at exercises
• PC Architectures and Expansion Buses
• Legacy ports
• USB
• Excluded topics
• Sections/details skipped during classes
• PC-Card Interface (L13-x)

7
Tutorial

• Selected questions from ET4508 / ED5532 Tutorial
  Sheets 1-3(http//www.ul.ie/rinne/et4508.htm)

8
Tutorial 1 Q4

• Superscalar processors use more than one pipeline
• Under best case conditions the Pentium can
  complete two instructions in every clock
• IA-32 instructions have to be paired according
  to Intel rules
• Pipeline u can execute any IA-32 instruction
• Pipeline v can execute simple instructions
• Pipeline u gets filled first
• If the second instruction is NOT part of a pair
  it waits for the next slot
• All pairing decoding decisions are done in
  hardware software support not required but
  helps performance

9
Tutorial 1 Q4
FP Pipeline has 8 stage Shares first 4 stages
with u integer pipeline WB of U is first
execution stage of FP pipline
10
Tutorial 1 Q5

• CISC Complex Instruction Set Computer
• Complex instructions. Code-size efficient
• Micro-encoding of the machine instructions
• Extensive addressing capabilities for memory
  operations
• Few, but very useful CPU registers
• CISC drawback Most instructions are so
  complicated, they have to be broken into a
  sequence of micro-steps
• These steps are called Micro-Code
• Stored in a ROM in the processor core
• Micro-code ROM Access-time and size...
• They require extra ROM and decode logic

11
Tutorial 1 Q5

• RISC Reduced Instruction Set Computer
• Sometimes executing a sequence of simple
  instructions runs quicker than a single complex
  machine instruction that has the same effect
• Reduce the instruction set to simplify the
  decoding
• Smaller Instruction Set -gt Simpler Logic -gt
  Smaller Logic -gt Faster Execution
• Eliminate microcode hardwire all instruction
  execution
• Pipeline instruction decoding and executing do
  more operations in parallel

12
Tutorial 1 Q5

• Load/Store Architecture only the load and store
  instructions can access memory
• All other instructions work with the processor
  internal registers
• This is necessary for single-cycle execution
  the execution unit cant wait for data to be
  read/written

13
Tutorial 1 Q5

• Increase number of internal register due to
  Load/Store Architecture
• Also registers are more general purpose and less
  associated with specific functions
• Compiler designed along with the RISC processor
  design. Compiler has to be aware of the
  processor architecture to produce code that can
  be executed efficiently

14
Tutorial 1 Q5

• Problem of given code sequence
• Register dependency
• Resulting in
• pipeline flush, temporary loss of performance
• Problem avoided by smart compilers

15
Tutorial 2 Q1

• Unified cache for code and data e.g. i486 More
  efficient use of resources
• Separate (Harvard) code and data caches e.g.
  Pentium
• Faster because you can access code and data in
  the same clock cycle

16
Tutorial 2 Q1

• Cache Hit if data required by the CPU is in the
  cache we have a cache hit, otherwise a cache miss
• Cache Hit Rate Proportion of memory accesses
  satisfied by cache, Miss Rate more commonly
  referred to
• To prevent memory bottlenecks cache miss rate
  needs to be no more than a few percent
• Cache Line A block of data held in the cache.
  Its the smallest unit of storage that can be
  allocated in a cache. Processor always reads or
  writes entire cache lines. Popular cache line
  size 16-32 bytes
• Cache Line Fill occurs when a block of data is
  read from main memory into a cache line

17
Tutorial 2 Q1

• Direct-mapped cache
• two different memory locations sharing the same
  set address cannot be held in the cache at the
  same time. They will contend

18
Tutorial 2 Q1

• Two-way Set-associative cache
• two different memory locations sharing the same
  set address can be held in the cache at the same
  time

19
Tutorial 2 Q1
20
Tutorial 2 Q1

• MESI Protocol
• Formal Mechanism for controlling cache
  consistency using snooping
• Every cache line is in 1 of 4 MESI states
  (encoded in 2 bits)

• ModifiedAn M-state line is available in only one
  cache and it is also MODIFIED (different from
  main memory). An M-state line can be accessed
  (read/written to) without sending a cycle out on
  the bus
• ExclusiveAn E-state line is also available in
  only one cache in the system, but the line is not
  MODIFIED (i.e., it is the same as main memory).
  An E-state line can be accessed (read/written to)
  without generating a bus cycle. A write to an
  E-state line causes the line to become MODIFIED

• SharedThis state indicates that the line is
  potentially shared with other caches (i.e., the
  same line may exist in more than one cache). A
  read to an S-state line does not generate bus
  activity, but a write to a SHARED line generates
  a write-through cycle on the bus. The
  write-through cycle may invalidate this line in
  other caches. A write to an S-state line updates
  the cache
• InvalidThis state indicates that the line is not
  available in the cache. A read to this line will
  be a MISS and may cause the processor to execute
  a LINE FILL (fetch the whole line into the cache
  from main memory). A write to an INVALID line
  causes the processor to execute a write-through
  cycle on the bus

21
Tutorial 2 Q1

• Data cache 2 bits required for encoding of 4
  possible states (MESI)
• Code cache inherently write protected. only 1
  bit required for 2 possible states (SI)