El' devices fabrication 2

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El. devices fabrication (2)
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Production of silicon

• Crystal growth
• - starting from electronic grade Si, obtained by
  distillation from metallurgical grade Si
• - Czochralski method -gt ingots (height 1m)

Then - cut -gt wafers (diam. 6 - 12 inches,
150-300 mm) - polishing (mechanical (abrasive)
chemical) Orientation (100) or (111)
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Photolithography (1/3)

• Photoresist (deposited via spinning)
• - negative (polymerize with UV)
• - positive (depolymerize with UV)

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Photolithography (2/3)

• - Photomasks (reticles)
• - normally 5x or 10x (with stepper -gt several
  exposures (each normally for more than one die)
• - or, mask 5x or 10x -gt stepped working plate
  -gt only one exposure, 1x
• - very expensive normally obtained via direct
  writing (electron beam lithography)

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Photolithography (3/3)

• Then, development (with organic solvents) to
  remove the non-polymerized photoresist
• Then, after the selective processing (deposition
  or etching), the photoresist is removed
• - chemically (with solvents), or with
• - reactive ion etching (ashing) plasma with
  oxygen
• If the mask has to withstand high T
• - not photoresist, but
• - SiO2 o Si3N4 (which, of course, are
  patterned using a photoresist)

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Oxide growth/deposition and removal

• - Oxide SiO2
• - easy growth/deposition
• - mechanically rugged readily dissolves in HF
• - excellent isolator -gt also for MOS
• Growth
• - dry Si O2 -gt SiO2
• - wet (not so good (superficial charge) but
  faster)
• Si 2H2O -gt SiO2 2H2
• - T 1000 oC
• - thickness 2x wrt Si (see LOCOS later)
• Alternatively deposition (not so good!). E.g.
  (its a CVD)
• SiH4 2NO2 -gt N2 2H2O SiO2

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Oxide

• Oxide removal
• - wet etching (with HF, isotropic)
• - dry etching (e.g. with reactive ion etching,
  e.g. trichloroethane Ar anisotropic -gt better
  control on the widths)

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Oxide

• Reactive ion etching
• LOCOS (local oxidation of silicon)
• selective growth of a very thick oxide
  normally for field oxide
• For Si3N4 CVD
• (chemical vapor deposition)
• 3SiH44NH3 -gt
• Si3N412H2

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Diffusions

• The planar process allows to build many devices
  simultaneously
• Diffusion
• - (pre)deposition
• - drive(-in)
• T 800-1250 oC
• Dopants
• Si-p B (B2H6)
• Si-n P (POCl3, PH3), As, Sb
• E.g.
• 4POCl33O2 -gt 2P2O56Cl2
• P2O5 builds a glass on Si
• 2P2O5 5Si -gt 4P5SiO2
• Poor control isotropic

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Diffusions

• Main parameters of the dopant
• - diffusion coeff.
• - solid solubility
• NB As, Sb have low diff. coeff.

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Diffusions

• Implantation
• (actually, it is not a diffusion...)
• high T not needed (-gt photoresist as mask)
• better control expensive and slow
• self-alignment (apart from straggle)!
• then, short annealing (T 800 oC) and, possibly,
  high T drive
• depth depends on V (and by the drive, if present)
• crystal tilt 7 deg

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Deposition of silicon (mono)

• To have a single crystal epitaxy
• - (rare liquid phase (with melted Si ))
• - low pressure chemical vapor deposition
  (LPCVD),
• SiH2Cl2 -gt Si 2HCl (with H2 as carrier), or
• SiCl42H2 -gt Si 4HCl or
• SiH4 -gt Si 2H2
• possibly with PH3 o B2H6 o AsH3 to dope
• - slow (1 mm/min) and expensive
• - T 1100 oC

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Deposition of silicon (poly)

• For polysilicon CVD
• SiH4 -gt Si 2H2
• e.g. on SiO2
• used
• - normally for MOS gates (withstands larger T
  wrt Al, and Vt is better controlled)
• - also for R (instead of diffused resistors)
• - also as a layer for (short) routing
• apparatus similar to the one for epitaxy

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Metallizations

• Example for single level metal
• Patterning
• - normal
• - lift-off (metal on the photoresist)
• On the contacts, Al dopes Si
• - ok for Si-p
• - for Si-n, Si-n is needed (see. Schottky
  junction)
• Al deposition
• - e.g via evaporation
• Some of Si in Al reduces the contact spiking (o
  emitter punchthrough)
• Some of Cu in Al reduces electromigration

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Metallizations

• To improve lateral coverage
• - reflow (before Al) high T, with P and B
  added to SiO2
• - refractory barrier metals (Mo, W (tungsten),
  Ti)
• Deposited via sputtering (they melt at too
  large T for evaporation)
• Also reduce contact spiking (and
  electromigration)
• But have poor conductance -gt sandwich with
  Al -gt
• e.g.. refractory metal, and Al with Cu (Si
  not needed)

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Metallizations

• Silicides Si metal (PtSi, Pd2Si, TiSi)
• - good ohmic contacts, or Shottky diodes
  moreover
• - low resistivity -gt for low resistivity poly
  (clad poly), e. g. for high speed MOS
• Ex of final sandwich PtSi refractory Al with
  Cu
• Also poly layers are often called metallizations

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And then...

• Between poly and metal1 multilevel oxide (MLO),
  with contact openings between metal1 and Si or
  Poly
• Between the various metals interlevel oxide
  (ILO), with vias between the various metals
• Above all protective overcoat (PO), or
  overglass, tipically Si3N4 (more resistent than
  SiO2), with openings for the pads

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Assembly and testing

• Often made in another facility (easy step -gt e.g.
  in the far east)
• Process control structures transistors, R, C,
  contacts
• Test dice variants of the IC, or to test
  subcircuits
• Test (wafer probing)
• of the wafer
• of each IC (t 3s yield 80)

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Assembly

• Then
• - cut
• - mounting on the leadframe (also for thermal
  exchange)
• - epoxy resin
• - soldering (also to have a substrate
  contact)

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Assembly

• Bonding (from bondpads to leadfingers)
• - Normally, 1 mil gold wire and ball bonding
• - for Al wedge bonding (similar, but the wire
  is snapped)
• - 10 per second!

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Assembly

• An IC with many
• leads...

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Packaging

• In plastic (injected from the bottom), or
  ceramic
• Then
• leads are cut and bent
• labels are added
• further test
• final packaging (tubes, reels)