ITRS 1999 International Technology Roadmap for Semiconductors

1
ITRS 1999International Technology Roadmap for
Semiconductors

• Chauchin Su
• Department of Electrical Engineering
• National Central University
• Chung-Li, Taiwan 32054
• ccsu_at_ee.ncu.edu.tw

2
Purposes

• Builds consensus on the future of technology
  requirements for maintaining the histroical rate
  of advancement out to a 15-year horizon.
• Focuses on the technology needs for main stream,
  leading-edge, silicon technology.
• Provides a snapshot of the current thinking of
  technologists and exposes opportunities for
  inventing new solutions.
• Intends to be a raodmap of technology needs, not
  solutions.

3
Whos who

• SIA - Semiconductor Industrial Association
• SCG - SIA Roadmap Coordinating Group
• SRC - Semiconductor Research Corporation
• SEMATECH
• TWG - Technology Working Group
• 7 Focus Technology Working Groups
• 4 Crosscut Technology Working Group

4
Technology Working Groups
Assembly/Package
The Focus TWGs
Front End Processing
Process Integrate, Device, Structure
Design and Test
Lithography
Interconnects
Factory Integration
Defect Reduction
The Crosscut TWGs
Environment, Safety, Health
Metrology
Modeling Simulation
5
The Focus TWGs

• Front End Process TWG
• Starting Materials (wafers)
• Surface Preparation
• Thermal/Thin Film and Doping
• Front End Etch
• Lithography TWG
• Exposure Equipment
• Resist Material and Processing Equipment
• Mask Making, Mask Equipment and Materials
• Process Integration, Devices, Structures
• Memory and Logic
• Analog and Mixed Signal
• Process Flow Methodologies
• Reliability Modeling and Testing

6
The Focus TWGs

• Interconnects
• Planarization
• Interconnect Architecture
• Interconnect Reliability
• Metals, Dielectrics, and Etch
• Design and Test
• Design Environment and Standard Interfaces
• System and IC Verification and Analysis
• Design Techniques and Methodologies
• System/Physical Design and Synthesis
• Testability
• Testing and Testers
• Known Good Die

7
The Focus TWGs

• Assembly and Packaging
• Multi/Single Chip Packaging
• Bonding Chip/Package/Substrate Design
• Packaging Substrates
• Thermal Power/Ground Management
• Electrical Performance Characterization
• Factory Integration
• Product and Material Handling
• Process and Equipment Control
• Operational Modeling and Simulation
• Manufacturing Information and Execution Systems
• Facilities Infrastructure
• Human Resources

8
The Crosscut TWGs

• Environment, Safety, Health (ESH)
• Chemical Management
• Natural Resource Management
• Worker Protection Tools
• ESH Design
• Metrology
• Critical Dimensions and Overlay
• Physical and Electrical Correlation
• Material and Contamination Characteristics
• Dopant Profile
• In situ Sensors for Process Control
• Film Thickness and Profile
• Reference Material

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The Crosscut TWGs

• Defect Reduction
• Defect Detection
• Yield Model and Defect Budget
• Defect Sources and Mechanisms
• Defect Prevention and Elimination
• Modeling and Simulation
• Equipment Modeling
• Feature-Scale Modeling
• Front End Process Modeling
• Lithography, Topography, Physical Device Modeling
• Circuit Element, Packaging Modeling
• Simulation Environment and Numerical Methods

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ITRS 1999 Summary
T Nodes Gate L (nm) DRAM HPitch Memory
Size Logic Size (Tx) On-Chip Clk Off-Chip Clk IC
Pins Min Vdd
2015 25 35 - 390M 16824 1852 3642 0.4
1999 140 180 256M 6.2M 1250 480 810 1.8V
2001 120 153 1G 10M 1500 785 900 1.5V
2003 100 130 1G 18M 2100 885 1100 1.2V
2006 70 100 4G 39M 3500 1035 1500 1.2V
2009 50 70 16G 84M 6000 1285 2000 0.9V
2012 35 50 64G 180M 10000 1540 2700 0.6V
High performance otherwise cost performance
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Grand Challenges

• The ability to continue affordable scaling
• Affordable lithography at and below 100nmNew
  material and structure
• GHz frequency operation on- and off-chip
• Metrology and Test
• The research and development challenge

12
Overall Test/Diagnosis Ability
250nm
Increase on chip test BIST/DFT
200nm
Standard Test Method for Core Based Designs
Timing/At-Speed Test at Core Level
150nm
Timing/At-Speed Test at Core Level
100nm
50nm
1997
1999
2001
2003
2006
2009
2012
13
Test Difficult Challenges
250nm
Fault Model Rules to Test Standard Test
Software DFT Failure Analysis
200nm
Mixed Signal Instrument BIST/DFT Probe Test
Socket IDDQ Testing Test Development Time
150nm
100nm
50nm
1997
1999
2001
2003
2006
2009
2012
14
Test Difficult Challenges gt 100nm

• BIST DFT Test equipment cost rise to 20M and
  yields fall to zero unless there is increased use
  of DFT/BIST.
• Probe Socket The major roadblock will be the
  need for high frequency, high pin count probes
  and sockets.
• Mixed Signal Instrument More bandwidth, higher
  sample rates and lower noise for RF/audio mixed
  signal ICs.
• IDDQ Testing Circuit partitioning and built-in
  current sensors are needed for gt 10M Tx.
• Test Development Time Mixed signal test
  development time must be reduced, analog DFT and
  BIST are key area for research.

15
Test Difficult Challenges lt 100nm

• Fault Model Stuck-at fault model is less
  effective, new model is needed.
• Rules to Test Tools and rules to automatically
  check the correctness of test program and DFT.
• Standard Test Software Common definition of test
  tools nomenclature to make tests portable are
  needed.
• DFT New DFT techniques other than SCAN and BIST,
  breaktrhough for control and observation are
  needed.
• Failure Anlysis 3D CAD and FA systems for
  isolation of defects in multi-layer metal
  processes.

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Yield v.s. Test Accuracy
1.6ns
250nm
1.2ns
200nm
0.8ns
150nm
0.4ns
100nm
50nm
1997
1999
2001
2003
2006
2009
2012
17
Package Difficult Challenges
250nm
Close gate between substrate chip System level
view of integrated chip, package, and substrate
200nm
150nm
Improve Organic Subtrate Improve
Underfills Reliability limited of flip
chip Integrated design tools
100nm
50nm
1997
1999
2001
2003
2006
2009
2012
18
Package Difficult Challenges gt 100nm

• gt 100nm
• Improve organic substrates for high I/O area
  array flip chip
• Improved underfills for high I/O area array flip
  chip
• Reliability limits of flip chip on organic
  substrates
• Integrated design tools and simulators to address
  chip, package, and substrate complexity
• lt 100nm
• Close the gap between the substrate technology
  and the chip
• System level view of integrated chip, package,
  and substrate needs.

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Integrated Design Environment
97
99
01
03
06
09
12
Physical Design Parameter-driven SCP system MCP
Floor Planning Parameter-driven MCP
place/route Electrical Design EMC
Interference Mixed Signal MCP Full wave
analysis Mixed electrical/optical Thermal Turbulen
ce in complex systems
Research
Development
Qualification
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Integrated Design Environment
97
99
01
03
06
09
12
Thermo-Mechanical Interface physics/models/data Fa
ilure mechanism based model Infrastructure Package
Model Common supplier data/framework Auto design
documentation Chip/Package/System
Integration Electrical Electrical/Thermal Elec
Thermal/thermal-mechanical Trade off/partitioning
system
Research
Development
Qualification