Computer Architecture From Many Perspectives

1
Computer Architecture From Many Perspectives

• Peter Hsu, Ph.D.
• Presented 13 September 2001 at Department
  dArquitectura de Computadors, Universitat
  Politècnica de Catalunya (UPC), Barcelona, Spain

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Industrys View

• Computer architecture vs. design?
• Tradition Architect creates a plan to transform
  clients desire into physical reality
• Interpretation
• Plan logical design, project schedule, cost
  projections,
• Reality mechanical, thermal, electrical issues
  reliability,
• Desire profit, return on investment

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Agenda

• Challenge to think more broadly about computer
  design
• Physics materials, signal integrity,
• Manufacturing tolerances, infrastructure,
• Financial design, fabrication costs,
• Interconnected-ness of issues, solutions
• Architect interface many different audiences
• Optimality depends of scope of view
• Novel solutions to current problems

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Presentation Methodology

• By examples
• Office environment multiprocessor server
• Mechanical, manufacturing issues
• Electrical signal, supply issues
• 3-D graphics chip for PC
• Project scheduling, costs, return on investment

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Caveats

• Authors bias performance
• ? latency (memory, inter-processor, etc.),
• ? bandwidth, then
• ? micro-architecture
• Decisions for presentation clarity
• Not advocating particular design
• No claims of right formula, ways of doing
  things
• One persons opinion your mileage may vary

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Example 1

• Office environment multiprocessor server
• Topics
• Interconnect/packaging scheme
• Manufacturability considerations ? performance
• Material characteristics ? micro-architecture
• Power supply
• Product usage environment ? micro-architecture

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Interconnect/Packaging

• Assumptions
• Multiple chips (more powerful than desktop)
• Not cheap (e.g. US50,000)
• Have control of CPU design
• i.e. Traditional computer system company
• Approach
• Low latency ? physically close together

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Multichip Module
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Chip Stack
12mm
0.3mm
router
10mm
DRAMs
processors
stack shown upside down
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Manufacturing Issues

• Stacking technology
• Limited production today, not discussed here
• Silicon substrate
• Process compatibility, availability
• Mechanically compliant connection
• Thermal expansion mismatch, reliability
• Repair strategy
• Inventory, product mix

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Silicon Substrate
12mm
4mm
maximum trace length 24.8cm
12mm chip
maximum cut-set 2048 p-to-p links
4mm spacer
200mm (8 inch) wafer
150?m pitch
3200 wire bonds substrate to PCB
14cm
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Stack to Substrate Connection
wirebond springs
heat
conventional wirebond pads
DRAMs
router chip
silicon substrate
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Mechanical Constraints

• Machined parts need several mils tolerance

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Implications

• Manufacturing infrastructure
• 64 stacks, 200mm wafer ? 1212mm die
• 250µm pad pitch ? 2304 pads
• Thermal density
• Stacked CPUs not feasible
• Goal low latency interconnect scheme in this
  context

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64?64 Full Crossbar?

• Tradeoffs
• ? Electrical delay off-chip crossings, data skew
• ? Logical latency contention, queuing
• ? Per-link bandwidth memory hot-spots
• Design
• Source Synchronous Links
• 8 data, 2 (differential) clock wires (20
  overhead)
• 63?2?10 ? 1260 signals / stack (45 power/ground)
• Cut-set 20,480 signals (track ? 7?m)

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Physics

• Delay ? distance (speed of light)
• Distant bandwidth ? wire pipelining ?
  transmission line ? low resistance
• R lt Z0 reflections, need terminator
• Z0 R 2Z0 self terminating
• 2Z0 lt R cannot wave pipeline
• Impedance Z0 is function of material, dimensions

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Basic Formulas
Bakoglu, H.B., Circuits, Interconnections, and
Packaging for VLSI, Addison-Wesley, 1990
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Design Challenge

• Materials
• Copper, ? ? 1.7 m??cm
• Low-K Insulator, ? ? 3.0
• Problem
• Cut-set ? narrow (4µm) wire
• Corner-to-corner ? 25mm
• Resistance 150O
• Impedance Z0 25O

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Interconnect Dimensions
width W
space S
pitch
4?
3.5?
7.5?
height H
6?
VDD
insulation thickness T
8?
VSS
2?
3?
5?
10?
4.5?
5.5?
15?
7.5?
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Substrate

• Features
• Self-terminating transmission lines
• 1? L ? 7.2cm R ? 51? Z0 ? 27?
• 2? L ? 18.4cm R ? 52? Z0 ? 26?
• 3? L ? 24.8cm R ? 47? Z0 ? 27?
• Integral power grid shielding, image current
• Sweet spot
• Fast sub- 2ns corner-to-corner
• High bandwidth 2 Gbits/s/wire
• Cheap 7 metal (3 XY ? pad) wafer, 2µm
  lithography

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Power Considerations

• Installation environment
• Home, office, server room?
• Heat Density
• Liquid cooling, heat pipe?
• Heat Dissipation
• Physical size, fan noise?

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Energy

• Office (USA)
• Peak 1300W
• Sustained 500W
• Human comfort
• Implications
• Stack ? 20W

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Implications

• Limit
• MHz
• CPU micro-architecture
• Memory bandwidth
• Router performance

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Example 2

• 3-D graphics chip for PC
• Topics
• Design cost
• Example numbers (huge variances!)
• Return on investment
• Impact on development cost

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Example Project Schedule
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Example Resource Needs
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Costs

• Development
• Approximation person year ? M
• 150K Salary 50 Benefits 50 Equipment 20
  Facilities
• Variation (20M - 200M) ? risk exposure
• Fallacy design cost ? design complexity
• Manufacturing
• 60mm2 die 10 (estimate 70 yield)
• Ball grid array package, assembly 5

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Return On Investment

• Factors
• Amount of money expended
• Time value
• Opportunity cost
• Reasonable ROI 5-10? after 4 years
• New development very risky compared to selling
  existing products
• Many, many non-technical risks

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Case Study

• PC graphics chip
• 20M development, 3 years
• 15 per-unit manufacturing cost
• Lifetime volume 2M units?
• Desired price 15 5(20M/2M units) 65
• Architecture impacts development cost e.g.
  super-pipeline ? circuit style ? CAD tools ?
  people resources

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Conclusion

• Industrial computer architecture plan mapping
  vision to reality
• Vision
• Performance goals micro-architecture, ROI,
• Reality
• Electrical, mechanical, thermal physics
  financial constraints peoples feelings
• Plan
• Convince me to bet on you authors opinion

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Comment

• As computer industry moves to System-On-a-Chip
  (SOC) products, there is a huge demand for
  computer architects that understand and are able
  to optimize in broad contexts.