CS 2200 Lecture 09b Hazards

1
CS 2200 Lecture 09bHazards

• (Lectures based on the work of Jay Brockman,
  Sharon Hu, Randy Katz, Peter Kogge, Bill Leahy,
  Ken MacKenzie, Richard Murphy, and Michael
  Niemier)

2
Control Hazards
3
R-Type
M X
1
P C
Instr Mem
DPRF
BEQ
A
Data Mem
M X
M X
D
SE
WB
EX
MEM
ID
IF
4
Control Hazard on BranchesTwo Stage Stall?
5
Example

• simulation

6
Scenario

• We have the following code segment
• lw R6, X(R0)
• beq R1, R2, SKIP
• add R1, R2, R3
• SKIP add R5, R4, R1
• sw R7, X(R0)
• X .word 5

7
lw R6,X(R0)
lw R6,X(R0) beq R1,R2,SKIP add
R1,R2,R3 SKIP add R5,R4,R1 sw R7,X(R0)
M X
1
P C
Instr Mem
DPRF
BEQ
A
Data Mem
M X
M X
D
SE
WB
EX
MEM
ID
IF
8
lw R6,X(R0)
beq R1,R2,SKIP
lw R6,X(R0) beq R1,R2,SKIP add
R1,R2,R3 SKIP add R5,R4,R1 sw R7,X(R0)
M X
1
P C
Instr Mem
DPRF
BEQ
A
Data Mem
M X
M X
D
SE
WB
EX
MEM
ID
IF
9
lw R6,X(R0)
beq R1,R2,SKIP
BUBBLE
lw R6,X(R0) beq R1,R2,SKIP add
R1,R2,R3 SKIP add R5,R4,R1 sw R7,X(R0)
M X
1
P C
Instr Mem
DPRF
BEQ
A
Data Mem
M X
M X
D
SE
Note Bubble because no branch predict or slot
fill.
WB
EX
MEM
ID
IF
10
lw R6,X(R0)
beq R1,R2,SKIP
BUBBLE
BUBBLE
lw R6,X(R0) beq R1,R2,SKIP add
R1,R2,R3 SKIP add R5,R4,R1 sw R7,X(R0)
M X
1
P C
Instr Mem
DPRF
BEQ
A
Data Mem
M X
M X
D
SE
Second bubble because were detecting BEQ in 3rd
stage.
WB
EX
MEM
ID
IF
11
lw R6,X(R0)
BUBBLE
BUBBLE
add R1,R2,R3
beq R1,R2,SKIP
lw R6,X(R0) beq R1,R2,SKIP add
R1,R2,R3 SKIP add R5,R4,R1 sw R7,X(R0)
M X
1
P C
Instr Mem
DPRF
BEQ
A
Data Mem
M X
M X
D
SE
WB
EX
MEM
ID
IF
12
beq R1,R2,SKIP
BUBBLE
add R1,R2,R3
BUBBLE
add R5,R4,R1
lw R6,X(R0) beq R1,R2,SKIP add
R1,R2,R3 SKIP add R5,R4,R1 sw R7,X(R0)
M X
1
P C
Instr Mem
DPRF
BEQ
A
Data Mem
M X
M X
D
SE
WB
EX
MEM
ID
IF
13
BUBBLE
add R1,R2,R3
BUBBLE
add R5,R4,R1
sw R7,X(R0)
lw R6,X(R0) beq R1,R2,SKIP add
R1,R2,R3 SKIP add R5,R4,R1 sw R7,X(R0)
M X
1
P C
Instr Mem
DPRF
BEQ
A
Data Mem
M X
M X
D
SE
Forwarding Unit
WB
EX
MEM
ID
IF
14
BUBBLE
sw R7,X(R0)
add R1,R2,R3
add R5,R4,R1
lw R6,X(R0) beq R1,R2,SKIP add
R1,R2,R3 SKIP add R5,R4,R1 sw R7,X(R0)
M X
1
P C
Instr Mem
DPRF
BEQ
A
Data Mem
M X
M X
D
SE
WB
EX
MEM
ID
IF
15
add R1,R2,R3
add R5,R4,R1
sw R7,X(R0)
lw R6,X(R0) beq R1,R2,SKIP add
R1,R2,R3 SKIP add R5,R4,R1 sw R7,X(R0)
M X
1
P C
Instr Mem
DPRF
BEQ
A
Data Mem
M X
M X
D
SE
WB
EX
MEM
ID
IF
16
add R5,R4,R1
sw R7,X(R0)
lw R6,X(R0) beq R1,R2,SKIP add
R1,R2,R3 SKIP add R5,R4,R1 sw R7,X(R0)
M X
1
P C
Instr Mem
DPRF
BEQ
A
Data Mem
M X
M X
D
SE
WB
EX
MEM
ID
IF
17
Summary

• Performance
• Execution time or throughput
• Amdahls law
• Multi-bus/multi-unit circuits
• one long clock cycle or N shorter cycles
• Pipelining
• overlap independent tasks
• Pipelining in processors
• hazards limit opportunities for overlap