TCSS 372A Computer Architecture

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TCSS 372A Computer Architecture

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Getting Started

• Get acquainted (take pictures)
• Discuss purpose, scope, and expectations of the
  course
• Discuss personal expectations strategy for
  doing well
• Review Web Page (http//faculty.washington.edu/lc
  rum)
• Review Syllabus, Textbook, and Simulator book
• Discuss Laboratory (CP 206D), Access, Etiquette,
  Equipment Check-out
• Discuss Homework Format
• Laboratory Report Format

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CSS 372 - Lecture 1

• Chapter 3 Connecting Computer Components with
  Buses
• Bus Structures
• Synchronous, Asynchronous
• Typical Bus Signals
• Two level, Tri-state, Wired Or
• Hierarchical Bus Organizations
• PCI Bus Example

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What is a Bus?

• A communication pathway connecting two or more
  devices (Computers, Components, I/O, )
• Usually broadcast
• Often grouped
• A number of channels in one bus
• e.g. 32 bit data bus is 32 separate single bit
  channels
• Power lines may not be shown

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What do Buses look like?

• Parallel lines on circuit boards
• Ribbon cables
• Strip connectors on mother boards
• Sets of wires

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Physical Realization of Bus Architecture
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Communication with Memory via a Bus
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Communication with I/O via a Bus
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CPU Communication via a Bus
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Data Bus (Subset of Bus)

• Carries data
• Remember that there is no difference between
  data and instruction at this level
• Width is a key determinant of performance
• 8, 16, 32, 64 bit

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Address Bus (Subset of Bus)

• Identify the source or destination of data
• e.g. CPU needs to read an instruction (data) from
  a given location in memory
• Bus width determines maximum memory capacity of
  system
• e.g. 8080 has 16 bit address bus giving 64k
  address space

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Control Bus (Subset of Bus)

• Control and timing information
• Memory read/write signal(s)
• Interrupt request/acknowledge signal(s)
• Clock signal(s)
• Etc.

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Power/Ground (Subset of bus ?)

• Provides Power and Reference Levels for Devices
• May be several voltage levels
• Ground may be dispersed between signals

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Types of Buses

• Dedicated
• - Separate data address lines
• Multiplexed
• - Shared lines
• - Address valid or data valid control line
• - Advantage - fewer lines
• - Disadvantages
• More complex control
• Ultimate performance

• Synchronous
• Asynchronous (Hand Shaking)
• Serial (Twisted pair, Coaxial Cable, ..)
• Parallel (Ribbon Cable, Bundle of Wires,)

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Physical Considerations for Buses

• Media (voltage, optic)
• Signal levels the higher, the more immune to
  noise
• Noise Absorption wires can pick up noise from
  neighboring wires
• Noise Generation wires can be antennas
• Length
• Creates Delay ( reduces Bandwidth)
• Consumes Power
• Creates reflections (Terminations
  become more critical)

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Logic Threshold Voltage Levels
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Signal Scheme Alternatives

• Totempole - High or Low output level
• Line always at a 1 level or 0 level
• Open collector, open drain, wired-or
• Line is nominally at a 1 level or 0 level
  line is pulled to non-nominal level
• Tristate
• Has third state open
• Differential
• Uses a pair of lines the level is the
  difference of signals on the two lines.

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Bus Challenges

• Lots of devices on one bus leads to
• Propagation delays
• Long data paths mean that co-ordination of bus
  use can adversely affect performance
• Traffic congestion
• Too many devices communicating reduces bandwidth
• Alternative - Systems use multiple buses

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Simple Computer Bus
clock(s), power(s), and
ground(s) Notes 1) Bus lines need to be
properly terminated 2) Power lines are
to furnish reference voltage, not power
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Adding an Expansion Bus
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Hierarchical Bus Structure
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Bus Arbitration

• More than one module may need to control the bus
• e.g. CPUs and DMA controller
• Only one module may control the bus at one time
• Arbitration may be centralised or distributed

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Centralised or Distributed Arbitration

• Centralised
• Single hardware device controlling bus access
• Bus Controller
• Arbiter
• May be part of CPU or separate
• Distributed
• More than one module may claim the bus
• Need control logic on all these modules

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Timing

• Co-ordination of events on bus
• Synchronous
• Events determined by clock cycles
• Control Bus includes clock line(s)
• A single 1- 0 sequence is a bus cycle (or phase)
• All devices can read clock line
• Likely they sync on leading edge
• Likely a single cycle for an event
• (may be multiple clock cycles or phases)

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Timing Diagram Conventions
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Synchronous Timing Diagram
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Asynchronous Timing Read Diagram
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Asynchronous Timing Write Diagram
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Example - PCI Bus

• Peripheral Component Interconnection
• Intel released to public domain
• 32 or 64 bit
• 50 lines

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Typical PCI Bus Usage
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Multiple PCI Bus Configuration
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PCI Commands

• Transaction between initiator (master) and target
• Master claims bus
• Determine type of transaction
• e.g. I/O read/write
• Address phase
• One or more data phases

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PCI Read Timing Diagram
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PCI Bus Arbiter
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PCI Bus Arbitration Timing