Design Optimization Based On Diagnosis Techniques

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Design Optimization Based On Diagnosis Techniques

• Yael Ohayon
• Oded Kiblitski

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Overview

• First part
• Background
• Logic optimization
• ATPG
• DEDC
• Second part
• The proposed research
• experiments
• conclusions

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Short Background

• Basic units (logic) wire, gate, bit
• Gate or, and, nor, xor
• Bit 0,1
• Mux selection unit
• Netlist collection of the basic units

01001...
or
M U X
and
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First steps in the design cycle
Verification
Tape out
Behavioral Description (RTL)
Logic synthesis
Logic Optimization
APR
Formal Verification
Static timing analysis
Extraction
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Logic optimization

• A step of the VLSI design cycle where the
  designer performs modification on the design.
• Most of the time the target logic is a single
  wire that violates some optimization constraints.

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Why do we need logic optimization?

• The objective is to modify the netlist to achieve
  different constraints such as

• minimize the area

• reduce power consumption

• satisfy timing constraints

• reduce switching noise

• improve the testability of the final circuit

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Design optimization via Rewiring

• Optimizing a given netlist with a sequence of
  logic transformation (adding/deleting a single
  wire or gate etc.)
• The optimization is based on removal and addition
  of logic without changing the netlist
  functionality

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Redundancy optimization

• One way to do automatic optimization is via
  redundancy addition removal.
• The method is to target a wire that violates
  certain specification constraints and attempt to
  remove it by
• Adding redundent logic.
• Blocking all possible paths that exist from the
  target wire to primary outputs.

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Redundancy optimization

• An example

Redundant Wire
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Redundancy optimization

• The removal of the Target Wire has made other
  wires redundant
• The gate count has been reduced leading to an
  optimized design

After Redundancy
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ATPGAutomatic Test Pattern Generator

• Generate test vectors from a given netlist
• The input is a netlist and a node in that netlist
  
• The outputs are
• A vector that that will show whether that node is
  stuck at one value.
• The expected results - a scalar

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Example
The node we are testing
S
M U X
The generated vector is 1,1,0
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DEDCDesign Error Diagnosis Correction

• DEDC is a way to fix problems found by ATPG
• In many cases a small number of modifications on
  a single line are sufficient to correct an
  erroneous design
• The input to the algorithm an erroneous design
  test vector
• The output list of all applicable corrections
• This list can be sorted by optimality of the fix,
  so we can pick the best fix to the problem

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DEDCDesign Error Diagnosis Correction

• Correction
• Compiles the list of all possible correction
• Keeps the correction iff it gives complemented
  logic values for each vector

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Summary (first part)

• Logic design optimization
• Design optimization via Rewiring
• redundancy addition removal

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Summary (first part)
Netlist (with susbect node)
(Test vectors) 01101 Expected results
ATPG
N O D E
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Summary (first part)
Erroneous design
Sorted list of corrections
DEDC
And Test Vectors
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• And now we are ready to introduce the new
• Logic Design Optimization

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Method Overview

• The proposed Optimization method is comprised of
  four main steps
• Introduce design error intentionally by removing
  the target logic
• Derive test vectors for this design error
• Use a DEDC algorithm to search for a correction
  that rectifies the design and pick the most
  optimal correction of all DEDC results
• Verify the correctness of the final design
• Now, we will cover the method step by step...

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Method Overview

• The first step of the algorithm artificially
  introduces a design error in the circuit by
  removing a target wire
• For example - a is late and we need another
  option for its connection

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Method Overview

• In the Second step, a 2-input mux is added, where
  the two input are the original design the
  erroneous one
• This is done in order to derive test vectors that
  detect the design error.
• The vectors are produced by the ATPG algorithm,
  where the MUX control is the node that we will
  test
• This will derive a vector(s) that distinguish
  between the correct and erroneous design

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Method Overview
All vectors, that a value is 1 And all other
values are the same
a b c
For example 1,0,0,0,0 1,1,1,1,1
Test vector?
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Method Overview

• In the third step, we run DEDC algorithm.
• The inputs are
• The original design
• The erroneous design
• Test vectors (derived in the second step)

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Method Overview
Original
Erroneous
?
DEDC
Test Vectors
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Method Overview

• The DEDC result Correction(s) that rectify the
  design for all test vectors (returned by the
  ATPG tool)

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Method Overview

• In the fourth last step we pick the most
  optimal solution and verify the correctness of
  the final design using ATPG
• we add a 2-input mux, where its inputs are the
  original design the final design
• we run ATPG on the new netlist in order to
  derive vector test

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Method Overview
S
Original
M U X
ATPG
Test vectors?
NONE!
Final
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The redundancy solution

• The solution returned by the proposed method
  cannot be found by a redundancy addition/removal
  optimization procedure
• Adding wire Wa is not redundant in presence of Wt

wt
wa
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Experiments

• Running 20 experiments on each circuit
• During each experiment we
• randomly picked and deleted an input wire to a
  gate
• counted the number of alternate wires that
  correct the design

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Experiments

• Experiments results

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Conclusions

• We presented an ATPG-based logic optimization
  methodology
• The methodology
• Target a wire that violates some optimization
  constraints
• remove the sub-optimal wire, and let DEDC find a
  better
• alternative implementation to this wire
• Guarantee the correctness of the final design

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Comments

• The method is only for a single-error case
• The DEDC is not a run-time efficient algorithm
• DEDC finds both the error and the solution.
• Why not use a correction algorithm (we know where
  the error is)

• But
• Its a new method based on a used proved
  methods
• It gives more correction options than the
  existing methods