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Chapter7' System Organization

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Intrasystem communication : within a single computer, primarily buses parallel ... ACKNOWLEDGE and resuming control of the system bus. ... – PowerPoint PPT presentation

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Title: Chapter7' System Organization


1
Chapter7. System Organization
2
System Organization
  • - How computers and their major components are
    interconnected and managed
  • at the system level.
  • 7.1. Communication Methods
  • 7.1.1 Basic concepts
  • Intrasystem communication within a single
    computer, primarily buses
    parallel
  • Intersystem communication electrical cables
    and optical fibers. serial

  • computer network.

3
Buses Physical links among the components as
well as the controlling mechanism
  • - A single system bus handles all intrasystem
    communication
  • At any time, only two units can
    communicate with each other.
  • CPU a bus master
  • M a bus slave
  • I/O devices normally a bus slave, but
    can be a bus master via IO processor
  • System bus address, data, and control
    lines
  • The characteristics of system bus closely
    matches those of its host CPU.

4
System bus High-speed data transfer between CPU
and M.
  • Most IO device are slower than CPU and M.
  • IO controllers that perform series-to-parallel
    and parallel-to-series
  • format conversions.
  • Standardized IO bus SCSI ( Small Computer
    System Interface )

5
Long-distance communication
  • Whereas intrasystem communication is serial by
    word, intersystem
  • communication is serial by bit due to the
    difficulty of synchronizing data bits
  • sent in parallel over long distances.
  • A sequence of many bits called a message is
    transmitted at one time.
  • When the pulses representing digital signal 0
    and 1 are transmitted over long
  • distances, the pulses may become unrecognizable
    due to the distortion caused
  • by noise.
  • More cost-effective to embed the data in analog
    signals for average
  • quality of transmission medium.

6
Computer networks Digital communication
networks designed to link many
independent computers to permit sharing of
computing resources.
  • Local area network (LAN) private data
    transmission links, Ethernet
  • Wide area network (WAN)
  • Techniques for sharing the communication links
  • Circuit switching
  • Message switching Use the intermediate
    servers to store messages and
  • subsequently forward them. Efficient
    utilization of links
  • Packet switching To solve the problem that
    the short messages can be delayed
  • while longer messages are being transmitted,
    divide messages into packets of
  • fixed length and format, and then transmit
    packets from long messages
  • interspersed with packets from short messages.
  • ATM ( asynchronous transfer mode ) combines
    voice and data
  • communication using short packets
    that can be transmitted very fast.

7
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The Internet A worldwide packet-switched
computer network descended from the
ARPANET.
  • IMP ( Interface Message Processor )
  • TCP/IP ( Transmission Control Protocol /
    Internet Protocol )
  • The Internet address is 4 bytes long
  • more than 4 billion distinct addresses.
  • An Internet packet is transmitted with a header
    containing its most recent source
  • address and its final destination address, as
    well as a sequence number indicating
  • its position in the original message. An Internet
    package can pass through dozens
  • of servers before reaching the target server.

9
Interconnection Structures
10
7.1.2. Bus Control
  • Two key issues
  • timing of transfers over the bus
  • the process by which a unit gains access to the
    bus
  • Synchronous communication The bus interface
    circuits of both the source
  • and destination units are synchronized.
  • disadvantage data-transfer rates are
    largely determined by the slowest
  • unit in the system.
  • Asynchronous communication local and long
    distance communication. Each
  • item is accompanied by a control signal that
    indicates its presence to the
  • destination unit. The destination unit responds
    with another control signal to
  • acknowledge. Data-transfer speed varies with the
    inherent speed of the
  • communication devices, at the cost of more
    complex control circuitry.

11
Bus interfacing A bus line represents a signal
path with potentially very large
fan-in and fan-out bus driver and bus receiver

12
Two big advantages of tristate logic circuits
The greatly increase the fan-in and fan-out
limits of bus lines, permitting very
large numbers of devices to be attached to the
same line. They support bidirectional
transmission over the bus by allowing the same
bus connection to serve as an input port
and as an output port at different
times.
13
Bus arbitration a selection mechanism to decide
among competing requests to the bus
at the same time. ?
Daisy chaining, polling, and independent
request. Daisy-Chaining
When the first unit receives the bus grant
signal, it blocks further propagation. The
unit closest to the bus-control unit has the
highest priority. Selection priority is
determined by the order in which the units are
linked by the Bus Grant lines. ?
susceptible to failure. Very
few control lines and a simple fixed arbitration
algorithm. A units priority cannot be
changed under program control. Can be used
with unlimited number of bus units.
14
Polling method
15
The Bus Grant line is replaced by poll count
line. Each unit compares a sequence of
numbers on the poll-count lines to a unique
address assigned to that unit. The priority
of a bus unit is determined by the position of
its address in the polling sequence. This
sequence can be programmed, hence priority can be
changed under software control. A
failure in one unit needs not affect the other
units. Require more control lines ( K
poll-count lines instead of one BUS GRANT line
) The number of units is limited by the
addressing capability of the poll-count lines.
16
Independent requesting
  • Priority is determined by the bus-control
    unit.
  • ? can respond very fast to request for
    bus access
  • To control n units, require 2n BUS REQUEST and
    BUS GRANT lines, compared
  • 2 lines for Daisy Chaining and log2n lines
    for Polling.

17
7.2. IO and System Control
  • IO control methods depending on how CPU is
    involved in I/O execution.
  • programmed IO IO operations are completely
    controlled by CPU.
  • require little or no special hardware,
    but causes CPU to spend a lot of
  • time for relatively trivial
    IO-related functions, such as testing the status
    of
  • IO devices.
  • DMA ( Direct Memory Access ) control IO device
    generates memory
  • addresses and transfer data to or from the bus
    connecting it to M without CPU
  • intervention.
  • The CPU and IO controller interact only when CPU
    must yield control of the
  • memory bus to the IO controller temporarily in
    response to requests from the
  • latter.
  • An interrupt request causes CPU to switch
    programs by saving its previous
  • program state and transferring control to a new
    interrupt-handling program.
  • IO processor has direct access to main memory,
    can interrupt CPU, and can
  • also execute IO programs directly without
    recourse to CPU.

18
Programmed IO for small, low-speed computer
systems
  • The IO device does not have direct access to M
    A data transfer from an
  • IO device to M requires CPU to execute several
    instructions.
  • IO addressing The address lines of the system
    bus for memory locations can also be used to
    select IO devices.
  • memory-mapped IO assign a part of main
    memory address to IO ports.
  • An instruction that causes data to be
    fetched from or stored at address X
  • automatically becomes an IO instruction
    if X is the address of IO port
  • no special IO instruction

19
  • IO-mapped IO the memory and IO address are
    separate
  • A memory-referencing instruction
    is different from an IO instruction.

20
DMA and Interrupts
  • The disadvantages of the programmed IO
  • The speed with which the CPU can test and
    service IO devices limits IO
  • data-transfer rates.
  • First, a delay occurs while an IO device
    needing service waits to be
  • tested by the CPU. If there
    are many IO devices in the system, each
  • device may be tested
    infrequently.
  • Second, programmed IO transmits data
    through the CPU rather than
  • allowing it to be passed
    directly from main memory to the IO device,
  • and vice versa.
  • The time that the CPU spends testing IO
    device status and executing IO data
  • transfers can often be better spent on
    other tasks.

21
  • In DMA, DMA REQUEST and INTERRUPT REQUEST connect
    IO devices to
  • CPU, cause CPU to suspend its current activities
    at appropriate breakpoints
  • and attend to DMA or interrupt request.
  • no need for CPU to execute routine testing.
  • A DMA request by an IO device only requires CPU
    to grant control of the
  • memory bus to the requesting device at the
    end of any transactions involving
  • the use of this bus.
  • Interrupt request asks CPU to begin executing an
    interrupt service program, in
  • addition to a request for bus control, similar
    to a subroutine call.

22
DMA
23
  • DMA controller contains a data buffer register
    IODR, an address register IOAR, and a data
    counter register DC, to transfer data to or from
    contiguous region of memory. The DMA controller
    sends an interrupt to CPU to signal the end of IO
    data transfer.
  • DMA block transfer transfer a sequence of
    arbitrary length in a single burst. The fastest
    IO data-transfer rates, but CPU may be inactive
    for relatively long periods by tying up the
    system bus.
  • Cycle stealing method allows the DMA controller
    to use the system bus to
  • transfer one data word, after which it must
    return control of the bus to CPU.
  • reduced IO transfer rate, also reduced
    interference by DMA controller.
  • Transparent DMA bus cycles are stolen only when
    CPU is not actually using the bus.

24
  • Process of DMA transfers
  • 1.The CPU executes two IO instructions, which
    load the DMA registers IOAR and
  • DC with their initial values. IOAR should
    contain the base address of the
  • memory region to be used in the data
    transfer. DC should contain the number of
  • words to be transferred to or from that
    region.
  • 2.When the DMA controller is ready to transmit or
    receive data, it activates the
  • DMA REQUEST line to the CPU. The CPU waits
    for the next DMA breakpoint.
  • It then relinquishes control of the data and
    address lines and activates DMA
  • ACKNOWLEDGE. Note that DMA REQUEST and DMA
    ACKNOWLEDGE
  • are essentially BUS REQUEST and BUS GRANT
    lines for control of the
  • system bus. Simultaneous DMA requests from
    several DMA controllers are
  • resolved by one of the bus-priority control
    techniques discussed earlier.
  • 3.The DMA controller now transfers data directly
    to or from main memory. After
  • a word is transferred, IOAR and DC are
    updated.
  • 4.If DC has not yet reached zero but the IO
    device is not ready to send or receive the
  • next batch of data, the DMA controller
    releases the system bus to the CPU by
  • deactivating the DMA REQUEST line. The CPU
    responds by deactivating DMA
  • ACKNOWLEDGE and resuming control of the
    system bus.
  • 5.If DC is decremented to zero, the DMA
    controller again relinquishes control of

25
  • Interrupts the primary means by which IO
    devices obtain the services of CPU.
  • Interrupts significantly improve a computers IO
    performance by giving IO
  • devices direct and rapid access to CPU and by
    freeing CPU from the need to
  • check the status of its IO devices.
  • The basic interrupt method is to activate
    INTERRUPT REQUEST that
  • connects the interrupt source to CPU.
  • The process of interrupt request
  • 1.The CPU identifies the source of the
    interrupt, for example, by polling IO
  • devices.
  • 2.The CPU obtains the memory address of the
    required interrupt handler. This
  • address can be provided by the
    interrupting device along with its interrupt
  • request.
  • 3.The program counter PC and other CPU status
    information are saved as in a
  • subroutine call.
  • 4.The PC is loaded with the address of the
    interrupt handler. Execution
  • proceeds until a return instruction is
    encountered, which transfers control
  • back to the interrupted program

26
Interrupt selection similar to bus arbitration
process.
27
Vectored interrupts The interrupting device
supplies CPU with the starting address or
interrupt vector of the interrupt-handling
program to get the most flexible response.
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7.2.3. IO Processors execute most IO
instructions
  • IO instruction type
  • READ a block of n words from device X to memory
    region Y
  • IOP is provided with direct access to M and so
    can control the memory bus
  • when CPU does not require that bus.

31
  • Three types of instructions executed by IOP
  • Data-transfer instructions. These include
    input (read), output (write ), and
  • sense (read status). They cause the number of
    bytes in the data count field
  • to be transferred between the specified
    memory region and the previously
  • selected IO device.
  • Branch instructions. These cause the IOP to
    fetch the next CCW from the
  • specified memory address rather than from the
    next sequential location.
  • IO device control instructions. These are
    transmitted to the IO device and
  • specify functions peculiar to that device.

32
IOP organization IOP and CPU share access to a
common memory M via the system
bus
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