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LEPS TPC Electronics

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Fixed target experiment with forward acceptance. ... Buffer depth: Nbit*Nslice*Nevt Fiducial. Zero-suppression: Yes. 11. AS Neutrino Exp (Texono) ... – PowerPoint PPT presentation

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Title: LEPS TPC Electronics


1
LEPS TPC Electronics
  • ???
  • Wen-Chen Chang
  • Institute of Physics, Academia Sinica
  • 03/30/2001

2
TPC inside LEPS Detectors
3
Experimental Environments
  • ?N??N, ?KN, ?N, ?N....
  • Fixed target experiment with forward acceptance.
    Occupancy is low, with at most 4-5 charged tracks
    per event.
  • Highest photon flux 10M/sec.
  • Triggering rate with 0.1 radiation target 1M
    /sec. (Most of them are ee- events.) The ee-
    events are expected to evade through the central
    pipe of TPC and will not come into the effective
    tracking volume.
  • Interaction of hadronic events (total cross
    section 1 mb) 1/1000 of ee- events 1k Hz. 1
    kHz DAQ rate required for recording all hadronic
    events. However, ?N??N rate is 0.01 mb.
  • Current DAQ rate is about 100Hz. Improvement will
    be done.

4
SPRing-8 Beam Structure
  • SPring-8 beam structure width of bunch 25 psec,
    minimum gap of bunch 2 nsec.
  • The circumference of the ring 1435.95 m 5000
    ns .
  • "24/29 filling" means that the ring is filled
    with bunches with 2 nsec separation for 24/29 of
    the ring like
  • lt----------------- one cycle
    ----------------------gt
  • 24/29 2ns bunches
    5/29
  • http//www.spring8.or.jp/ENGLISH/schedule/2000sche
    dule-e.html.
  • The closest beam bunch in time is 2 nsec.

5
TPC Mechanical Specification
  • Inner radius lt 1.25 cm.
  • Outer radius lt 30 cm.
  • Maximum drift distance 70 cm.
  • Maximum drift time 14 ?sec with drift velocity
    5 cm/?sec.
  • Read out channels 95 sensing wires, 1000 pads.
  • Geometric size of pads two types(?).
  • Separation of sensing wire 4mm.

6
Requirement of TPC Electronics
  • Determine dE/dx from the charge readout of
    either wires or pads.
  • Requirement of spatial resolution
  • x,y lt 250 ?m.
  • z lt 1 mm.
  • Position information
  • x(t),y(t) from the x and y of fired sense wires
    and pads(t).
  • z(t) from time bin of FADC time slice.
  • Timing information fitting of pulse peak in
    FADC?.
  • On-board zero-suppression to ensure fast data
    transfer and short system dead time.

7
TPC Electronic Pre-Amp
  • Directly hooked to the endplate of TPC.
  • ATLAS TGC ASD Chip
  • http//onlax2.kek.jp/sosamu/ASD-PRR.pdf.
  • Gain 0.8 V/pC.
  • Integration time 16 nsec.
  • Pulse lengthen 100 nsec.
  • ENC7500 electrons at Cd150 pF.

8
TPC Electronic Main-Amp
  • For trigger determination.
  • Differential signal input.
  • Discriminator and Shaper.
  • Output pulse width lt 200 ns.
  • Gain ??
  • Module NIM, CAMAC or on FADC board.
  • Output V range 0-2 V.
  • DO we need this part?

9
TPC Electronic FADC
  • Sampling rate 40 MHz 25 nsec ? (by fitting,
    peak determination) 5 nsec 0.25 mm (spatial
    resolution) 20 MHz 50 nsec ? 10 nsec 0.5 mm
    .
  • Read-out bit (Nbit) 8-10 bits, depending on the
    charge resolution and identification of low
    momentum K,p by dEdx.
  • of Time bins per event 700 bins.
  • trigger latency/clock 1 usec/25 nsec 40 bins.
  • max drift time/clock 15 usec/25 nsec 600 bins.

10
TPC Electronic FADC
  • Event Size/per channel 8bit700700 bytes.
  • Event Size w/o zero suppression
    0.7KB100020KB(header)720KB0.72MB.
  • LEPS DAQ transfer rate 3MB/sec.
  • Transfer dead time 0.72/30.24 sec.
  • Buffer depth NbitNsliceNevtFiducial.
  • Zero-suppression Yes.

11
AS Neutrino Exp (Texono)
  • Measuring energy loss of neutrinos in CsI crystal
    via PMT.
  • Main-Amp (no Pre-Amp)
  • Preserving time shape.
  • Gain Ki3.2 V/mA, Kv64.
  • Vout 0-2.8 V.
  • Negative signal input, differential output.
  • NIM module, 16 channels/per mod.
  • 900 USD/per mod.

12
BESII upgrade at IHEP, Bejing (I)
  • FADC
  • 40 MHz (?22.5 MHZ) 8 bits readout.
  • On-board DSP for zero-suppression.
  • Single event rate lt 354 Hz.
  • Maximum firing rate (2k-3k Hz).
  • Spatial resolution 0.5 mm.
  • 16-32 channels/ per board.

13
BESII upgrade at IHEP, Bejing (II)
  • TDC using CERN HPTDC chip.
  • Dead time free, high resolution, 32 chan/per
    chip.
  • 66 USD/per chip.
  • Status and Schedule
  • 2-channel test board, done.
  • pre-prototype, 09/2001.
  • prototype, 12/2001.
  • With Main-Amp, summer of 2002.

14
Information Needed
  • 1. Bombard rate 1K Hz for total hadronic
    events.
  • 2. Trigger latency time for making trigger
    decision? lt 1 micro-sec.
  • 3. Trigger rate data-taking rate lt 100 Hz (10
    dead time)
  • 4. Signal rate per channel how frequent a
    channel fires? 1KHz or more ? This depends on
    track density.
  • 5. Signal width from TPC Is it mainly
    determined by the pre-amp? something like a
    couple hundred nsec.
  • 6. Maximum drift time 70cm/(5cm/micro-sec) 14
    micro-sec.
  • 7. Required time resolution(sigma, in ns)
    contributed by electronics say, less than 1mm,
    1mm/(5cm/micro-sec)20 nsec.
  • 8. Required integrated non-linearity for time
    measurement???

15
Questions
  • 9. Maximum charge value to be measured
    depending on how many electrons will be collected
    and the gain of Pre-amp.
  • 10. Required charge resolution contributed by
    electronics less than the single bit of FADC.
  • 11. Required integrated non-linearity for charge
    measurement depending on the ADC specification.
  • 12. Channel number for time measurement for
    sense wires about 100 channels
  • 13. Channel number for charge measurement for
    pad channels about 1000 channels.
  • 14. Required on-board pre-processing items?????

16
Questions
  • 15. Inherent chamber spatial(position)
    resolution we need calculation about the
    diffusion of electron clusters when they drift
    toward the pads. We need the pressure and B field
    strength for the estimation.
  • Typical sigma(x,y)100-200 ?m, sigma(z)0.2-1
    mm.
  • 16. Electron drift velocity in the TPC gas about
    5 cm/micro-sec
  • 17. Allowed dead time 10 dead time?.
  • 18. Multi-hit ability for each channelYes,
    because of the spiral motions of low momentum
    tracks.

17
Events
  • Prof. Imai and Ahn visited AS on
    02/09/2001-02/10/2001. Collaborating plan was
    discussed and finalized.
  • AS group will prepare the electronic modules for
    June testing.
  • Kyoto and RCNP group will prepare the VME (6U-9U)
    and CAMAC crates.
  • The DAQ interface cards are purchased and FADC
    modules, Clock module, Calibration module and
    logic control module are being built.
  • Appendix of NSC 2001 proposal is submitted on
    03/19/2001.
  • Wen-Chen and Henry will discuss with IHEP group
    on 03/31-04/02.
  • IHEP group will send one expert to be stationed
    at AS in this summer.
  • Maybe a student from Kyoto group will go to AS
    some time for setting up electronics, DAQ and
    event display for June test.

18
Plan and Milestones
  • Up to 06/01/2001 construction of TPC mechanical
    parts.
  • 06/01/2001-12/31/2001 testing of TPC using
    TEXONO FADC modules and DAQ system.
  • 12/31/2001 Construction of prototype of new FADC
    module at IHEP, Bejing.
  • 01/01/2002-01/31/2002 Testing of prototype FADC
    module.
  • 02/01/2002-04/30/2002 Mass production of new
    FADC modules.
  • 05/02/2001-06/30/2002 Delivery of FADC modules
    to Spring-8 and installation.
  • 07/02/2001-08/32/2001 Electronics system test.
  • 09/01/2001 Data-taking starting at Spring-8.
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