ManUfacturability, Test, and Diagnostics for Microelectronics

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ManUfacturability, Test, and Diagnostics for
Microelectronics

• Summer Semester 2009Dr. Bernd KoenemannProf.
  Dr. Walter AnheierDr. Ajoy Palit

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About Me

• 1974 Diplom-Physiker, TU Braunschweig
• 1977 Dr. rer. nat., TU Braunschweig
• 1978-80 RWTH Aachen (ITHE, Prof. W. Engl)
• 1980-84 Honeywell, Minneapolis MN
• 1984-95 IBM, Poughkeepsie/East Fishkill NY
• 1995-99 LogicVision, San Jose CA
• 1999-02 IBM, San Jose CA
• 2002-04 Cadence Design Systems, San Jose CA
• 2004-05 Mentor Graphics, San Jose CA
• 2005- Dolce Far Niente, San Jose CA/
  Bremen/Cartagena de Indias

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Web Presence and E-Mail

• Professional
• http//www.testviewz.com
• Presentations, papers
• Personal
• http//www.koenemann.org
• Photos, videos, music
• Contact
• bernd_at_koenemann.org

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Reading Material
EDA for IC System Design, Verification, And
Testing Luciano Lavagno, Grant Martin (Editor),
Lou Scheffer (Editor) Published March
2006 ISBN-10 0849379237 ISBN-13 9780849379239
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Overall Context
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Design

• Design derives implementations from
  specifications
• Refinements, e.g.,
• Register Transfer Level (RTL) to gate-level,
  gate-level to schematic
• Transformations, e.g.,
• Gate-level/schematic to physical
• Design Flow
• Collection/sequence of tools and design steps
• A complete flow derives a final implementation
  from the original design intent
• The final implementation is used for
  manufacturing, e.g.,
• Layout data in GDSII format
• Test data

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Design Verification

• Design Verification validates the correctness of
  the design descriptions at each design step, e.g,
  by
• Simulation
• Static verification
• Layout Versus Schematic (LVS)
• Physical Design Rules Check (DRC)
• Ideally, Design Verification proves that the
  final implementation matches the original Design
  Intent
• Implementation Design Intent!

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Manufacturing Test/Silicon Verification

• Manufacturing test validates that the hardware
  matches the final implementation
• Hardware final implementation!
• Silicon verification validates that the hardware
  operates according to the design intent
• Hardware design intent!

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Layout

• The logic and/or analog design structures must be
  translated into geometrical shapes and layers for
  mask making

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CMOS NAND-Gate
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Source D. Pan, University of Texas
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Full Custom Design Style
Source D. Pan, University of Texas
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Standard Cell Design Style
Source D. Pan, University of Texas
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Gate Array Design Style
VDD
Metal1
Metal2
Structured ASICs (hot topics nowadays) are
essentially gate array
Source D. Pan, University of Texas
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FPGA Design Style
Source D. Pan, University of Texas
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Scaling Roadmap
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Source ITRS 2001
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Metal Stack
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Whats the Problem?
Perfectby design ???
Lost inTranslation
Defects !!!