Manufacturability, Test, and Diagnostics for Microelectronics

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Manufacturability, Test, and Diagnostics for
Microelectronics

• Summer Semester 2009Dr. Bernd KoenemannProf.
  Dr. Walter AnheierDr. Ajoy Palit

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Overall Context
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Memory BIST and Diagnostics
SS 2007
Automatic Test and Diagnostics for
Microelectronics

• Have to add data logging capabilities to the BIST
  engine
• Typically uses a real-time pass/fail signal
• May use serial TAP interface for logging detailed
  fail data
• E.g., BIST status registers, fail bit registers

Address
Data In
Data Out
Addr
Din
Serial Interface
BIST Controller
TAP
R/W
RAM
Dout
Data logging
Pass/fail
Compare
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Physical Bitmap Pattern Examples

• After translation from logical to physical
  coordinates

Vertical PairBit Line Contact
Partial ColumnResistive Bit Line Short
Multi-RowAddress Decoder
SwatchCMP Scratch
Entire BitSense amp, I/O
CatastrophicTiming Circuit
From R. Aitken, Artisan
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Built-In Self Repair
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Logic Diagnostics Context
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Logic Diagnostics

• Finding the root-cause of a particular test fail
• Characterizing the failing behavior
• Localizing the most likely problem area
• Integral part of
• Silicon debug
• Failure analysis
• Logic diagnostics are more complicated
• Irregular structures
• Less controllability/observability (only scan
  cells and PIs/POs)

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Example
From A. Weber, Semi International, 2004
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Logic Diagnostics and Failure Analysis

• Log some number of fail sets from test
• Run logic fault isolation software
• Create gate-level callouts (net/pin names, fail
  type) most likely near the problem area
• Visualize callouts in layout
• Requires link between gate-level netlist and
  layout (e.g., from running LVS)
• Overlay callouts with defect maps or other
  information
• Requires translation to/from wafer-level
  coordinates
• Initiate Failure Analysis (FA)

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High-Level Flow
Tests
Source D. Lavo, UCSC
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Fail Set

• Collection of fail signatures
• Test vector ID, failing response bits (scan cells
  or POs)

Fail Signature 1 4, 5
Source D. Lavo, UCSC
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Fault Isolation Software
Netlist,Fault Models
Fault Simulation
Simulatedfail sets
TestPatterns
Compareandrank
Callouts
ATE/BIST
Fail sets
Note Fault simulation can be run ahead of time
to pre-calculate a fault dictionaryor after the
fact during diagnostics
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Fault Dictionaries

• A fault dictionary is a database of the simulated
  responses for all faults in faultlist
• Simulated Fail Sets
• Used by some diagnosis algorithms for
  convenience
• Fast no simulation at time of diagnosis
• Self-contained netlist, simulator, and test set
  not needed after dictionary creation
• Can be very large, however!

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Source D. Lavo, UCSC
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Post-Test Simulation

• Alternative to dictionary-based diagnosis
• Fault simulation is only done for certain faults,
  based on test results
• Only simulate faults in input cones of failing
  flip-flops/outputs
• Dictionary is eliminated, but requires complete
  netlist and test pattern file
• Used by most commercial ATPG tools Mentor
  Fastscan, Synopsys, Cadence, etc.

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Source D. Lavo, UCSC
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Fault Isolation Components
Select Faults
Netlist Import
Netlist
Callout Report
Fault Callout
Fail Data Import
Fail Set
Diagnostic Fault Simulation
Select Patterns
Test Data Import
TestVectors
Callout Analysis
Source T. Bartenstein, Cadence Design Systems
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Diagnostic Fault Simulation

• Simulate selected faults over selected patterns
• Compare effects of faults with failure data
• Score faults based on how well they match fails
• Produce Diagnostic Callout
• List of scored faults
• Detail information on score components
• Callout used for
• Graphical Analysis
• Callout report
• Automated callout analysis (defect reasoning)

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Source T. Bartenstein, Cadence Design Systems
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CalloutS

• Ranked list of possible fault location candidates

Note from IBM TestBench
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Non-Stuck-At Defects
SS 2007
Automatic Test and Diagnostics for
Microelectronics

• Not all defects behave exactly like stuck-at
  faults
• How can fault isolation with stuck-at faults work
  on other defects?
• One Answer Single-Location-At-A-Time Paradigm
• Many defects behave like a stuck-at fault for one
  failing test at a time, but
• May behave like a different fault or
  inconsistently in other patterns
• Composite behavior may indicate non-stuck-at type
  of fail behavior

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Example Bridging Defects
SS 2007
Automatic Test and Diagnostics for
Microelectronics
A-sa0
B-sa0
B-sa0
B-sa1
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Callout Analysis

• Fault Composites
• Derive information about un-modeled defects by
  combining information about two or more modeled
  faults
• Several ways to composite
• Stuck-at-X (composite of stuck-at-1 and
  stuck-at-0)
• Slow to rise and fall (composite of slow to rise
  and slow to fall)
• Multiple fault analysis
• Single Pattern Diagnostics
• Find faults which explain single failing test
  patterns
• Find signatures of un-modeled failure mechanisms
  from the results
• Assumes defect behavior is dependent on circuit
  state

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Source T. Bartenstein, Cadence Design Systems
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Failure Analysis
Source Cadence Design Sytems
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Time 328 ps
0?1
Source IBM Corp.
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Time 482 ps
Source IBM Corp.
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Time 865 ps
Source IBM Corp.
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The finding

• 45 mismatch between reality and simulation
• Had been marginal in previous technology Newer
  technology more sensitive

Source IBM Corp.
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Research Areas In Fault Isolation
SS 2007
Automatic Test and Diagnostics for
Microelectronics

• Better classification of non-stuck-at behaviors
• Better correlation to circuit-level schematics
  and layout
• Better correlation to Design For Manufacturing
  (DFM)
• Handling of compressed responses from test data
  compression

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The New Role of Test

• Classical Yield Management Systems provide lots
  of wafer-level information, but lack intra-chip
  resolution
• Test observes chip-internal fail behavior that
  could help uncover the statistical impact of new
  catastrophic and parametric defect sources inside
  the chips
• By adding statistical analysis capabilities, test
  can become a key tool for statistical
  design/yield learning

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Statistical Diagnostics for Logic

• Emerging defect/yield learning method for complex
  logic designs
• Implement comprehensive fail set logging for
  initial ramp and for volume production test
• Run logic fault isolation on all fail sets (could
  be thousands per day)
• Write all callout information into database
• Statistically sort, analyze, and visualize the
  cumulative callout information, e.g.,
• Query by cell-type, cell-instance/location,
  design features, etc.
• Stack results on chip layout, reticle, and/or
  wafer map
• Compare with yield predictions
• Etc.

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Example Sorting by Cell Type
Relative occurrencenormalized to occupied area
60
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40
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10
0
NOR
Buffer
Inverter
Flip-Flop
AND-OR
Multiplexer
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FromD. Apello, et al., ST Micro
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Example Coding by Cell Location

• Statistical analysis of single-net failures

Cell a
Cell b
Cell c
Cell d
Cell e
Probability
From D. Appello, et al., ST Micro, Synopsys
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Underlying Problem
FromD. Appello, et al., ST Micro, Synopsys
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Example Stacked Callout Visualization
Note from LSI Logic
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Design for Manufacturing (DFM)

• Extend design closure objectives from timing,
  area, and power to manufacturability
• Defect-limited yield (random and systematic)
• Circuit-limited yield
• Process window
• Short-term correct-by-construction operations
• Shape fill, redundant via addition, wire
  spreading
• Long-term Incorporate DataPrep Simulation
  downstream analysis into Design

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Examples of Shape Fill for CMP
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Shape Fill Effect
SS 2008
Automatic Test and Diagnostics for
Microelectronics
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Redundant Via Aware Routing - Basics

• Yield loss due to via failure
• Complete vs. partial failure gt functional and
  parametric yield loss
• Redundant via (RV) insertion is an effective
  technique to improve yield (recommended by fab)

Dead via
Degree of freedom (DOF) DOF(A) 1 DOF(B)
0 DOF(C) 3
On-track candidate
Off-track candidate
Live via
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RV Consideration During Routing

• Adapt wiring layout for improved redundant via
  insertion

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Wire Spreading
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Effect of Wire Spreading/Widening

• Critical area before and after spreading/widening
  of wires

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Our Agenda for the SEmester
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