VLSI Design Flow

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VLSI Design Flow
Lecture 3 Sept 10, 2002 Presented by Andy
Laffely alaffely_at_ecs.umass.edu
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Goal

• The course will cover basic theory and techniques
  of digital VLSI design in CMOS technology. Topics
  include CMOS devices and circuits, fabrication
  processes, static and dynamic logic structures,
  chip layout, simulation and testing, low power
  techniques, design tools and methodologies, VLSI
  architecture. We use full-custom techniques to
  design basic cells and regular structures such as
  data-path and memory. There is an emphasis on
  modern design issues in interconnect and
  clocking. We will also use several case-studies
  to explore recent real-world VLSI designs (e.g.
  Pentium, Alpha, PowerPC StrongARM, etc.) and
  papers from the recent research literature.
  On-campus students will design small test
  circuits using various CAD tools. Circuits will
  be verified and analyzed for performance with
  various simulators. Some final project designs
  will be fabricated and returned to students the
  following semester for testing. (4 credits)

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Lecture Overview

• TA web page
• General design flow
• Introduce tools with a NOR gate example
• Digital Integrated Circuits A Design
  Perspective, J. Rabaey, Prentice-Hall, 1996,
  first edition, ISBN 0-13-178609-1. Web Page for
  the book including Powerpoint and PDF of all
  slides, MAGIC, SPICE, etc. (Important list of
  errors (Errata) in the book) Note that the second
  edition of the textbook will be available in
  October 2002, however this course will use the
  first edition.

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Terminology

• Layout
• Mask

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TA Pagewww.ecs.umass.edu/ece/vspgroup/burleson/co
urses/558/orhttp//vsp2.ecs.umass.edu/vspg/658/T
A_Tools/index.html

• TA inforamtion
• Different tools for Grad and Undergrad
• Useful links for
• Models and Tools
• Design rules
• Hand calculation parameters
• Examples!!!!
• ETC

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Design Methodology

• Full Custom The designer creates layout masks by
  hand.
• Potentially fastest and most power efficient
  designs
• Long design cycle
• Standard Cell The designer uses high level
  programing language to describe the system and
  lets the computer make the masks.
• Shorter design cycle
• Less efficient designs

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• The full custom flow can produce very compact
  layouts, which run fast, but doing so can be
  involved. Using standard cells greatly reduces
  designer workload, but the resulting
  implementations can have wasted area and
  typically run slower. The following design flow
  and links are intended to introduce you to the
  tools involved. Each link contains an example of
  the approach or a tool you may use.Full Custom
  There is a nor and example in the vlsix58.tar.gz
  file with all the steps complete.
• Architecture Design The first step is the
  architecture design. VerilogXL allows you to
  specify and test your system at the behavioral
  level.
• Logic Design Using the Cadence schematic editor
  in icms, you can develop and extract a schematic
  of your system. Logic verification can be done
  with either VerilogXL or IRSIM, a simple logic
  simulator. Both require modifications to the
  extracted netlist, but these perl scripts should
  do it nicely. (schm2vlog.pl for Verilog) or
  (schm2sim.pl for IRSIM). The Cadence tool icms
  also has a the to simulate a design using
  Verilog. I have found this to be cumbersome, but
  you may attempt this by reviewing the process in
  cdsdoc (AMS tools).
• Circuit Design This differs from logic design in
  that you must now account for the electrical
  properties of the devices. The first step is to
  calculate the approximate size of the transistors
  by hand calculations. After this, modify the
  properties of the transistors in your schematic
  to match your calculations. Verify both the speed
  and power consumption of your design using either
  extracted netlists and hspice or Spectre inside
  icms. (schm2spice.pl will help modify the
  extracted netlist for hspice)
• Layout Design After your schematic is verified
  and simulated you will actually build the mask
  layers in the layout editor. Now you must perform
  2 steps to assure your layout works properly.
• - First you should verify the logic. You can do
  this using the layout vs. schematic option in
  layoutPlus or by extracting the circuit and
  running either Verilog (via lo2vlog.pl) or IRSIM
  (via lo2sim.pl).- After verifying the
  functionality, you should re-simulate the system
  for performance using hspice (via lo2spice.pl).
• Standard Cell Design Architecture Design The
  first step is the architecture design. VerilogXL
  allows you to specify and test your system at the
  behavioral level.
• Layout Synthesis You will use 2 tools
• - Synopsys will link your verilog code to the
  standard cell library. The result is a netlist of
  standard cells.- Silicon Ensemble takes the
  netlist and places and routes the cells.
• Layout Verification and Simulation After the
  layout is generated you can use the tools to
  verify and simulate your system.
• - First you should verify the logic. You can do
  this by extracting the circuit and running either
  Verilog (via lo2vlog.pl) or IRSIM (via
  lo2sim.pl).- After verifying the functionality,
  you should extract with parasitics and simulate
  the system for performance using hspice (via
  lo2spice.pl).

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Design Flow

• System Level Design
• Logic Design
• Logic Verification
• Circuit Desgn
• Performance Evaluation
• Layout
• Logic Verification
• Performance Evaluation

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System Design

• Goal Create a high-level (Behavioral)
  representation of your system
• Tools Verilog, VHDL, System C
• Synthesizable (PLDs and/or ASIC)
• Non-synthesizable
• More in future lectures

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Logic Design and Verification

• Translate system level discription into
  transistors
• Many logic styles
• Schematic representation
• Logic verification
• Simplistic models - to verify functionality
• Fast - can run many cases
• 558 - Use DSC2
• 658 - Use Cadence Schematic HSPICE

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Circuit Design

• Calculate trasnsistor sizes
• Performance evaluation
• Complex models - to evaluate timing and power
• Slow - run only selected cases
• 558 - Use Microwind
• 658 - Use HSPICE

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Layout

• Translate schematic into layout
• Need to know the design rules
• Layout representation may not be similar to
  schematic
• Logic verification
• Compare netlists
• Simulators
• Performance evaluation
• Use detailed simulations
• 558 - Use Microwind
• 658 - Use Cadence Vertuoso, IRSIM, HSPICE

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