1um CMOS Process Baseline Electrical Test Summary

1
1um CMOS Process BaselineElectrical Test Summary

• Georgia Tech
• Microelectronics Research Center

2
Summary Package Outline

• Overall Summary - pages 3 - 8
• Front End Summary - pages 9 - 65
• test structure description and methodology
• theoretical expected value
• measured value results
• Back End Summary - pages 66 - 110
• test structure description and methodology
• theoretical expected value
• measured value results

3
CMOS Baseline summary

• Overall Summary of CMOS baseline
• NMOS transistor yield is 30 for 3um lt L lt 25um.
  Below 3um yield falls to 20 due to punch-thru.
• PMOS transistor yield is 25 for 3um lt L lt 25um.
  Below 3um yield falls to 5 due to punch-thru.
• Many front end parameters have median values
  close to target however standard deviation is
  high as can be seen in pass on summary page or
  in the raw data throughout the presentation.
• Contact parameters are the most off target and
  would be the first area to address in improving
  the CMOS line. (Contact experiment has since
  been completed. See separate presentation
  summary for results).
• What is the baseline?
• The baseline consists of 5 batches with a total
  of 37 wafers. Each batch was processed
  individually and separately between 2001 - 2003
  timeframe in the MiRC cleanroom.
• Batch 6 showed the best overall performance
  across all parameters and notably had a 60 NMOS
  transistor yield and 70 PMOS transistor yield.

4
Front Back End Summary
Contact parameters are the parameters which are
most off target, followed by field oxide
thickness, NMOS threshold voltage, and M1
serpentine Resistance.
5
Overall Transistor Yield
NMOS
PMOS
Note that transistor yield shows a dependency on
channel length. For channel lengths 3um and
greater yield is fairly constant. For channel
lengths 2um and lower, the yield degrades due to
punchthru. Transistor Yield is defined as
threshold voltage, saturation current, and off
current all being in control limits for a given
die. The of good die on a wafer can then be
calculated and averaged over all of the batches.
6
NMOS PMOS Off Current (A)W10 ?m, Lvarying,
Log10 scale
NMOS
PMOS
punch-thru
Below channel length of 3um, the OFF state
current increases rapidly. The current shown is
the current from the source due to the bias at
the drain. Therefore it is punch-thru. (This
data is from batch 6 wafer 6 and is typical of
the baseline.)
7
NMOS PMOS IDS VS. VDS CURVESW/L 10um/3um
NMOS
PMOS
IDS vs. VDS curves are shown from one of the
better performing batches (Batch 6 wafer 1) from
a W/L 10um/ 3um transistor . At, VDSVGS5V,
NMOS and PMOS saturation current is 1.14mA and
0.35mA respectively. Normalizing for transistor
width (W10um), NMOS and PMOS saturation currents
are 0.114mA/um and 0.035mA/um respectively.
8
Subthreshold Slope and Drain InducedBarrier
Lowering (DIBL)
NMOS
PMOS
Sub-threshold curves are shown from one of the
better performing batches (Batch 6 wafer 1). NMOS
and PMOS sub-threshold slopes are both
150mV/decade. NMOS and PMOS DIBL are 10mV/V and
20mV/V respectively.
9
Front End Parameter Summary

• Front End Parameters which are analyzed in this
  presentation are listed below and are covered on
  slides 7-61.
• N, P, Poly sheet resistance
• Poly CD
• Poly COMB leakage
• Poly serpentine resistance
• NMOS PMOS gate oxide thickness
• N-Well P-Well field oxide thickness
• NMOS PMOS
• Threshold Voltage
• Saturation Linear current
• Off current

10
N Sheet Resistance Structure
3
5
7
9
1
wide structure (216.5 ?m long x 4.5 ?m wide)
Van der pauw structure
8
10
2
4
6
There are two N sheet resistance measurements
made. One is made on the wide structure, the
other is made on the Van der pauw structure. A
maximum current of 100mA is forced (IF) between
pads 9 and 1 with an applied 1V, and a voltage
drop is measured (VM) at pads given in the table
below.
11
N Sheet Resistance Theoretical Value
The NS/D As Implant has a dose of 5.74E19/cm3
and a junction depth of 1.6um after 1 hour of
annealing at 950C.
12
N Sheet Resistance Theoretical Value
? q(n?n p?p)
for N-type material,
? ? qn?n
? ? 1/?
For NS/D, a 5E15, 160keV As implant is used, and
a 1 hr anneal at 950C is performed Therefore n
5.74E19 cm-3 and xj 1.6?m
? ? 1/(1.6E-19 C)(5.74E19 cm-3 )(23 cm2/V-s)
? 4.7E-3 ??cm
Rs ? / xj
(4.7E-3 ??cm) / (1.6E-4 cm)
Rs 29.6 ?/
P.M.Rousseau, et.al., A Model for Mobility
Degradation in Highly Doped Arsenic Layers, IEEE
Transactions on Electron Devices, vol. 43,
p.2025, 1996.
13
N Sheet Resistance (?/?) Measured ValueVan der
Pauw Method, Target 30 ?/?
Full Scale ?
Target 30 ?/
0 to 150 ?/? ? Scale ?
14
N Sheet Resistance (?/?) Measured Value Wide
structure method, Target 30 ?/?
Full Scale ?
Target 30 ?/? ?
0 to 150?/? Scale ?
15
N Sheet Resistance (?/?) Measured ValueVan der
pauw Method compared to Wide Method
Unity line
Theoretical Target 30 ?/ ? ?
The Van der pauw method data seems aberrant as it
is several orders of magnitude higher than the
Wide method and it appears to get worse with
higher resistance values. It seems that the Wide
method is more accurate as it produces more
values closer to the theoretical target. In
either case, both methods show there are many die
with excessively high sheet resistance.
16
N Sheet Resistance (?/ ? ) Measured ValueSummary
Mean 47.8 ?/ ? ? Target 30 ?/ ? ? Average
Pass 63
Using the Wide Method data, the mean of all the
wafer medians is 47.8 ?/?, excluding wafers with
values marked in red. Using a LCL 3 and UCL
150, the average of good die for a given wafer
is 61 (no wafers excluded).
17
P Sheet Resistance Structure
3
5
7
9
1
wide structure (217 ?m long x 4.5 ?m wide)
Van der pauw structure
8
10
2
4
6
There are two P sheet resistance measurements
made. One is made on the wide structure, the
other is made on the Van der pauw structure. A
maximum current of 100mA is forced (IF) between
pads 9 and 1 with an applied 1V, and a voltage
drop is measured (VM) at pads given in the table
below.
18
P Sheet Resistance Theoretical Value
? q(n?n p?p)
for P-type material,
? ? qp?p
? ? 1/?
For PS/D, a 5E15, 30keV B11 implant is
used, Therefore n Cp 4.6E20 cm-3 and xj
0.100?m
? ? 1/(1.6E-19 C)(4.6E20 cm-3 )(35 cm2/V-s)
? 3.9E-4 ??cm
Rs ? / xj
(3.9E-4 ??cm) / (1E-5 cm)
Rs 39 ?/
G.Masetti, et.al., Modeling of Carrier Mobility
Against Carrier Concentration in Arsenic-,
Phosphorus-, and Boron-Doped Silicon, IEEE
Transactions on Electron Devices, vol. 30, p.764,
1983.
19
P Sheet Resistance (?/?)Van der Pauw Method,
Target 39 ?/?
Full Scale ?
Target 39 ?/?
0 to 120 ?/? Scale ?
20
P Sheet Resistance (?/?)Wide structure method,
Target 39 ?/?
Full Scale ?
Target 39 ?/?
0 to 120 ?/? Scale ?
21
P Sheet Resistance (?/?) Measured ValueVan der
pauw Method compared to Wide Method
Unity line
Theoretical Target 39 ?/?
The Van der pauw method data seems aberrant as it
is several orders of magnitude higher than the
Wide method and it appears to get worse with
higher resistance values. It seems that the Wide
method is more accurate as it produces more
values closer to the theoretical target. In
either case, both methods show there are many die
with excessively high sheet resistance.
22
P Sheet Resistance (?/?) Measured ValueSummary
Mean 49.3 ?/? Target 39 ?/? Average Pass
48
Using the Wide Method data, the mean of all the
wafer medians is 49.3 ?/?, excluding wafers with
values marked in red. Using a LCL 3 and UCL
120, the average of good die for a given wafer
is 48 (no wafers excluded).
23
Poly Sheet Resistance Structure
3
5
7
9
1
wide structure (217 ?m long x 6 ?m wide)
narrow 1 CD
Van der pauw structure
narrow 2 CD
8
10
2
4
6
narrow 1 CD structure (202.5 ?m long x 2 ?m
wide)
narrow 2 CD structure (245 ?m long x 2 ?m wide)
24
Poly Sheet Resistance Theoretical Value
Rs 49 ?/
25
Poly Sheet Resistance (?/?)Van der Pauw Method,
Target 49 ?/?
Full Scale ?
Target 49 ?/?
0 to 150 ?/? Scale ?
26
Poly Sheet Resistance (?/?)Wide structure
method, Target 49 ?/?
Full Scale ?
Target 49 ?/?
0 to 150 ?/? Scale ?
27
Poly Sheet Resistance (?/?) Measured ValueVan
der pauw Method compared to Wide Method
Unity line
Theoretical Target 49 ?/?
The Van der pauw method data seems aberrant as it
is several orders of magnitude higher than the
Wide method and it appears to get worse with
higher resistance values. It seems that the Wide
method is more accurate as it produces more
values closer to the theoretical target. In
either case, both methods show there are many die
with excessively high sheet resistance.
28
Poly Sheet Resistance (?/?) Measured ValueSummary
Mean 44.3 ?/? Target 49 ?/? Average Pass
53
Using the Wide Method data, the mean of all the
wafer medians is 44.3 ?/?, excluding those wafers
with values marked in red. Using a LCL 3 and
UCL 150, the average of good die for a given
wafer is 53 (no wafers excluded).
29
Poly CD Narrow 1 2 (?m)Target 2?m
Full Scale ?
Full Scale ?
30
Poly CD Narrow 1 2 (?m)Target 2?m
0 to 10?m Scale ?
0 to 10?m Scale ?
31
Poly CD Narrow 1 2 comparison
Unity line
Target 2 ?m
There does not appear to be a printing bias
between CD Narrow 1 2.
32
Poly CD Narrow Summary
Mean 3.4 ?m Target 2 ?m Average Pass 56
The mean of all the wafer medians is 3.4 ?m,
excluding those wafers with values marked in
red. Using a LCL 0.1 ?m and UCL 6 ?m, the
average of good die for a given wafer is 56
(no wafers excluded).
33
Poly COMB Serpentine Structure
3
5
7
9
1
8
10
2
4
6
left comb
serpentine
COMB Serpentine 1
COMB Serpentine 2 (duplicate of 1)
Poly CD 2?m Space 2?m serpentine length
6,764?m
right comb
34
Poly COMB Serpentine
The serpentine poly line is connected to pad 5
10 on structure 2 and pad 1 6 on structure
1. The purpose of the serpentine structure is
to measure its resistance and monitor for opens
due to incomplete patterning. The serpentine is
long and winding in order to make it susceptible
to lithography and etch patterning problems. A
poly comb lies on either side of the serpentine
poly. The comb is electrically isolated from the
serpentine line. The purpose of the comb is to
measure leakage current between it and the poly
serpentine and monitor for shorts. Shorts
would be caused by remaining poly electrically
connecting the comb to the poly serpentine line.
On structure 2, pads 7 9 connect to the comb
to the left of the serpentine and pad 8 connects
to the comb to the right of the serpentine. On
the structure 1, pad 3 connects to the comb on
the left of the serpentine, and pads 2 4
connect to the comb on the right of the
serpentine.
35
Poly COMB leakage (A)Target 1E-12 A
A good die from Batch 3, Wafer 4 was compared to
a bad die from Batch 5 wafer 4. The findings are
presented on the next slide.
36
Poly COMB Good vs. Bad comparison
GOOD
BAD
Batch 3, wafer 4, die (5,8)
Batch 5, wafer 4, die (4,6)
Space not visible between Poly lines. Lines are
shorted together. CONCLUSION Polysilicon
lithography either underdeveloped or
underexposed. Not a problem with Etching.
Space visible between Poly lines.
37
Poly COMB Summary
Mean 1.3E-12 A Target 1E-12 A Average Pass
66
The mean of all the wafer medians is 1.3E-12A,
excluding those wafers with values marked in
red. Using a LCL 0 and UCL 1E-9, the average
of good die for a given wafer is 66 (not
excluding any wafers).
38
Poly Serpentine Resistance (?)Target 166 k?
Poly CD 2?m serpentine length
6,764?m 6,764?m /2?m 3,382 3,382 (49 ?/?)
166k ? Target 166k ?
39
Poly Serpentine Resistance (?) Summary
Median 184 k? Target 166 k? Average Pass
33
The median of all the wafer medians is 184 k?,
excluding wafers whose values are marked in
red. Using a LCL 16 k? and UCL 497 k? , the
average of good die for a given wafer is 47
(not excluding any wafers).
40
Gate Field Oxide Structure
3
5
7
9
1
100 ?m x 100 ?m
8
10
2
4
6
The PMOS Gate N-Well Field structures are in a
row adjacent to the row shown above with an
identical layout except for it is in an N-Well
region and the S/D diffusion is P.
41
NMOS Inversion Gate Oxide Thickness (Å)Target
300 Å
Full Scale ?
200 to 1000 Å Scale ?
42
NMOS Inversion Gate Oxide Thickness Summary
Mean 320 Å Target 300 Å Average Pass 37
The mean of all the wafer medians is 320 Å,
excluding the wafers with values in red. Using a
LCL 200 Å and UCL 400 Å, the average of
good die for a given wafer is 37, not excluding
any wafers.
43
PMOS Inversion Gate Oxide Thickness (Å)Target
300 Å
Full Scale ?
200 to 1000 Å Scale ?
44
PMOS Inversion Gate Oxide Thickness Summary
Mean 304 Å Target 300 Å Average Pass 22
The mean of all the wafer medians is 304 Å,
excluding the wafers with values in red. Using a
LCL 200 Å and UCL 400 Å, the average of
good die for a given wafer is 22, not excluding
any wafers.
45
N and P-Well Accumulation Field Oxide Thickness
(Å)Target 6500 Å
6500 Å Target
P-Well ?
6500 Å Target
N-Well ?
46
N-Well Accumulation Field Oxide Thickness Summary
Mean 2689 Å Target 6500 Å Average Pass 2
The mean of all the wafer medians is 2689 Å,
excluding the wafers with values in red. Using a
LCL 5500 Å and UCL 7500 Å, the average of
good die for a given wafer is 2, not excluding
any wafers.
47
P-Well Accumulation Field Oxide Thickness Summary
Mean 3173 Å Target 6500 Å Average Pass 6
The mean of all the wafer medians is 3173 Å,
excluding the wafers with values in red. Using a
LCL 5500 Å and UCL 7500 Å, the average of
good die for a given wafer is 6, not excluding
any wafers.
48
Transistor Structure
3
5
7
9
1
8
10
2
4
6
All NMOS PMOS transistors have the same basic
layout as above for W 5, 10, 50 um. Each row
contains a unique L. Shown above is L 25?m.
The variations of L are 1, 1.3, 1.5, 2, 3, 5, 10,
25 ?m. So there are 2 (NMOS/PMOS) x 8(various L)
16 rows. In each row there are 3 transistors,
so there are 3 x 16 48 unique transistors.
49
NMOS PMOS Threshold Voltage (V)W5 ?m,
Lvarying
For each wafer L varies from left to right in
the following order 1, 1.3, 1.5, 2, 3, 5, 10, 25
?m.
50
NMOS PMOS Threshold Voltage (V)W10 ?m,
Lvarying
For each wafer L varies from left to right in
the following order 1, 1.3, 1.5, 2, 3, 5, 10, 25
?m.
51
NMOS PMOS Threshold Voltage (V)W50 ?m,
Lvarying
For each wafer L varies from left to right in
the following order 1, 1.3, 1.5, 2, 3, 5, 10, 25
?m.
52
NMOS Vt value and Pass by Channel Width/Length
Mean 147 mV Target 0.7 V Average Pass 55
W50?m is offset towards 0
Yield degrades below L3?m
The mean of all the wafer medians is 147 mV,
excluding the wafers with values in red. Using a
LCL 0V and UCL 3V, the average of good die
for a given wafer is 55, not excluding any
wafers.
53
PMOS Vt value and Pass by Channel Width/Length
Mean -608 mV Target -0.7V Average Pass 48
Yield degrades below L3?m
The mean of all the wafer medians is -608
mV. Using a LCL -3V and UCL 0V, the average
of good die for a given wafer is 48. No wafers
were excluded in either calculation.
54
NMOS PMOS Saturation Current (A)W5 ?m,
Lvarying, Log10 scale
For each wafer L varies from left to right in
the following order 1, 1.3, 1.5, 2, 3, 5, 10, 25
?m.
55
NMOS PMOS Saturation Current (A) W10 ?m,
Lvarying, Log10 scale
For each wafer L varies from left to right in
the following order 1, 1.3, 1.5, 2, 3, 5, 10, 25
?m.
56
NMOS PMOS Saturation Current (A) W50 ?m,
Lvarying, Log10 scale
For each wafer L varies from left to right in
the following order 1, 1.3, 1.5, 2, 3, 5, 10, 25
?m.
57
NMOS IDsat value and Pass by Channel
Width/Length
A Pass was calculated using a LCL of 1E-6A.
58
PMOS IDsat value and Pass by Channel
Width/Length
A Pass was calculated using a LCL of 1E-6A.
59
NMOS PMOS Off Current (A)W5 ?m, Lvarying,
Log10 scale
For each wafer L varies from left to right in
the following order 1, 1.3, 1.5, 2, 3, 5, 10, 25
?m.
60
NMOS PMOS Off Current (A)W10 ?m, Lvarying,
Log10 scale
For each wafer L varies from left to right in
the following order 1, 1.3, 1.5, 2, 3, 5, 10, 25
?m.
61
NMOS PMOS Off Current (A)W50 ?m, Lvarying,
Log10 scale
For each wafer L varies from left to right in
the following order 1, 1.3, 1.5, 2, 3, 5, 10, 25
?m.
62
NMOS IOFF value and Pass by Channel Width/Length
A Pass was calculated using an UCL of 1E-6A.
63
PMOS IOFF value and Pass by Channel Width/Length
A Pass was calculated using an UCL of 1E-6A.
64
Overall Transistor Yield
PMOS
NMOS
Overall Transistor Yield was calculated by
requiring each die to pass the control limits for
Vt, Idsat, and Ioff simultaneously.
65
W10?m Transistor Yield by Batch
PMOS
NMOS
66
Back End Parameter Summary

• Back End Parameters which are analyzed in this
  presentation are listed below and are covered on
  slides 63-106.
• N, P, Poly, single contact resistance
• N, P, Poly contact chain resistance
• Single VIA1 and chain VIA1 resistance
• M1 and M2 sheet resistance and CDs
• M1 comb leakage and serpentine resistance

67
N Contact Resistance Structure
3
5
7
9
1
3?m x 3?m contact
8
10
2
4
6
68
N/P Contact Resistance Theoretical Value
using ND6E20cm-3 and ?B0.72
Then rc 0.1? is the target N and Poly contact
resistance. (Since Poly has similar sheet
resistance as N, the Schottky Barrier height and
doping is assumed to be close to the same and
therefore the Poly Contact resistance is also
assumed to be close to the same.)
using NA4.6E20cm-3 and ?B0.58
Then rc 1? is the target P contact resistance.
W.R.Runyan, K.E.Bean, Semiconductor Integrated
Circuit Processing Technology, 1st edition,
p.522-524, 1990.
69
N Contact Resistance (?)Target 0.1 ?
N Contact Resistance is very high.
70
N Contact Resistance Value and Pass
Mean 2E9 ? Target 0.1 ? Average Pass 8
The mean of all the wafer medians is 2E9 ?. Using
a LCL 0.001 and UCL 100, the average of
good die for a given wafer is 8.
71
N Contact Chain Structure
3
5
7
9
1
104 contacts
8
10
2
4
6
There are 104 contacts, 100.2 squares of N
diffusion, and 77.8 squares of M1. Using the
theoretical values of N contact resistance, N
sheet resistance and M1 sheet resistance found
elsewhere in this document the theoretical target
value for N contact chain is 5.0k?.
72
N Contact Chain Resistance (?)Target 5k ?
73
N Contact Chain Resistance Value and Pass
Mean 6E10 ? Target 5 k? Average Pass 28
The mean of all the wafer medians is 6E10
?. Using a LCL 1k ? and UCL 100k ?, the
average of good die for a given wafer is 28.
74
P Contact Resistance Structure
3
5
7
9
1
8
10
2
4
6
75
P Contact Resistance (?)Target 1 ?
P Contact Resistance is very high.
76
P Contact Resistance Value Pass
Mean 6E8 ? Target 1? Average Pass 15
The mean of all the wafer medians is 6E8 ?. Using
a LCL 0.1 ? and UCL 100 ?, the average of
good die for a given wafer is 15.
77
P Contact Chain Structure
3
5
7
9
1
8
10
2
4
6
There are 104 contacts, 100.2 squares of P
diffusion, and 77.8 squares of M1. Using the
theoretical values of P contact resistance, P
sheet resistance and M1 sheet resistance found
elsewhere in this document the theoretical target
value for N contact chain is 4.0k?.
78
P Contact Chain Resistance (?)Target 4 k?
79
P Contact Chain Resistance Value and Pass
Mean 5.3E10 ? Target 4 k? Average Pass 52
The mean of all the wafer medians is 5E10
?. Using a LCL 1k ? and UCL 100k ?, the
average of good die for a given wafer is 52.
80
Poly Contact Resistance Structure
3
5
7
9
1
8
10
2
4
6
81
Poly Contact Resistance (?)Target 0.1 ?
82
Poly Contact Resistance Value and Pass
Mean 2.4E10 ? Target 0.1? Average Pass 11
The mean of all the wafer medians is 2.4E10
?. Using a LCL 0.1 ? and UCL 100 ?, the
average of good die for a given wafer is 11.
83
Poly Contact Chain Structure
3
5
7
9
1
8
10
2
4
6
There are 104 contacts, 100.2 squares of Poly,
and 77.8 squares of M1. Using the theoretical
values of Poly contact resistance, Poly sheet
resistance and M1 sheet resistance found
elsewhere in this document the theoretical target
value for Poly contact chain is 4.9k?.
84
Poly Contact Chain Resistance (?)Target 4.9 k?
85
Poly Contact Chain Resistance Value and Pass
Mean 1.3E11 ? Target 4.9k? Average Pass
22
The mean of all the wafer medians is 1.3E11
?. Using a LCL 1k? and UCL 100 k?, the
average of good die for a given wafer is 22.
86
M1 Sheet Resistance Structure
3
5
7
9
1
wide structure (215 ?m long x 9 ?m wide)
narrow 1 CD
Van der pauw structure
narrow 2 CD
8
10
2
4
6
narrow 1 CD structure (203 ?m long x 3 ?m wide)
narrow 2 CD structure (244 ?m long x 3 ?m wide)
87
M1 M2 Sheet Resistance Theoretical Value
For Aluminum with 1 Silicon, the resistivity is
? ? 3.4E-6 ??cm
Rs ? / xj
(3.4E-6 ??cm) / (6000 E-8 cm)
Rs 56.7 m?/ for M1
for M2, xj 8000Å so Rs 42.5 m?/
W.R.Runyan, K.E.Bean, Semiconductor Integrated
Circuit Processing Technology, 1st edition,
p.535, 1990.
88
M1 Sheet Resistance (m?/)Van der Pauw Method,
Target 56.7 m?/
Full Scale ?
30 to 90 m?/ Scale ?
89
M1 Sheet Resistance (m?/)Wide Structure Method,
Target 56.7 m?/
Full Scale ?
30 to 90 m?/ Scale ?
90
M1 VDP Sheet Resistance Value and Pass
Mean 57.2 m?/ Target 56.7 m?/ Average
Pass 70
The mean of all the wafer medians is 57.2 m?/,
excluding the wafers with values in red. Using a
LCL 10 m?/ and UCL 100 m?/ , the average
of good die for a given wafer is 70, not
excluding any wafers.
91
M1 CD Narrow 1 2 (?m)Target 3?m
92
M1 CD Value and Pass
Mean 4.1 ?m Target 3 ?m Average Pass 47
The mean of all the wafer medians is 4.1 ?m,
excluding the wafers with values in red. Using a
LCL 1 ?m and UCL 5.5 ?m , the average of
good die for a given wafer is 47, not excluding
any wafers.
93
M1 COMB/SERP Structure
3
5
7
9
1
8
10
2
4
6
left comb
serpentine
COMB Serpentine 1
COMB Serpentine 2 (duplicate of 1)
M1 CD 3?m Space 3?m serpentine length
4,504?m
right comb
94
M1 COMB/SERP
95
M1 COMB leakage (A) Target 1E-12A
96
M1 COMB leakage Value and Pass
Mean 1E-12A Target 1E-12A Average Pass 82
The median of all the wafer medians is
1E-12A. Using a LCL 0 and UCL 1E-9, the
average of good die for a given wafer is 82.
97
M1 Serpentine Resistance (?)Target 85 ?
Full Scale ?
10 to 200 ? Scale ?
98
M1 Serpentine Resistance Value and Pass
Mean 200 ? Target 85 ? Average Pass 63
The mean of all the wafer medians is 200 ?,
excluding the wafers with values in red. Using a
LCL 10 ? and UCL 450 ? , the average of
good die for a given wafer is 63, not excluding
any wafers.
99
M2 Sheet Resistance Structure
3
5
7
9
1
wide structure (216 ?m long x 9 ?m wide)
narrow 1 CD
Van der pauw structure
narrow 2 CD
8
10
2
4
6
narrow 1 CD structure (203 ?m long x 3 ?m wide)
narrow 2 CD structure (244 ?m long x 3 ?m wide)
100
M2 Sheet Resistance (m?/)Van der Pauw Method,
Target 42.5 m?/
Batch 4 5 did not receive M2 processing
Full Scale ?
Batch 4 5 did not receive M2 processing
30 to 90 m?/ Scale ?
101
M2 Sheet Resistance (m?/)Wide Structure Method,
Target 42.5 m?/
Batch 4 5 did not receive M2 processing
Full Scale ?
Batch 4 5 did not receive M2 processing
30 to 90 m?/ Scale ?
102
M2 VDP Sheet Resistance Value and Pass
Mean 45.8 m?/ Target 42.5 m?/ Average
Pass 92
Batch 4 5 did not receive M2 processing
The mean of all the wafer medians is 45.8 m?/,
excluding batch 4 5. Using a LCL 10 m?/ and
UCL 100 m?/, the average of good die for a
given wafer is 92, excluding batch 4 5.
103
M2 CD Narrow 1 2 (?m)Target 3?m
Batch 4 5 did not receive M2 processing
Batch 4 5 did not receive M2 processing
104
M2 CD Narrow 1 Value and Pass
Mean 3.0 ?m Target 3 ?m Average Pass 54
Batch 4 5 did not receive M2 processing
The mean of all the wafer medians is 3.0 ?m,
excluding the wafers with values in red. Using a
LCL 1 ?m and UCL 5.5 ?m , the average of
good die for a given wafer is 54, excluding
batch 4 5 only.
105
M2 to M1 Via Structure
3
5
7
9
1
M1
M2
8
10
2
4
6
106
M2 to M1 Via Resistance (?)Target 0.1 ?
Batch 4 5 did not receive M2 processing
Full Scale ?
Batch 4 5 did not receive M2 processing
0 to 20 ? Scale ?
107
M2 to M1 Via Resistance (?)
Mean 13.7 ? Target 0.1 ? Average Pass 53
Batch 4 5 did not receive M2 processing
The mean of all the wafer medians is 13.7 ?,
excluding the wafers with values in red. Using a
LCL 0.1 ? and UCL 100 ? , the average of
good die for a given wafer is 53, excluding
batch 4 5 only.
108
M2 to M1 Via Chain Resistance Structure
3
5
7
9
1
8
10
2
4
6
There are 104 VIAs, 77.8 squares of M1, and 104
squares of M2. Using the theoretical values of
VIA resistance, M1 M2 sheet resistance found
elsewhere in this document the theoretical target
value for VIA chain is 19?.
109
M2 to M1 Via Chain Resistance (?)Target 19 ?
110
M2 to M1 Via Chain Resistance Value and Pass
Mean 4E11 ? Target 19 ? Average Pass 0.4
The mean of all the wafer medians is 13.7 ?,
excluding the wafers with values in red. Using a
LCL 0.1 ? and UCL 100 ? , the average of
good die for a given wafer is 53, excluding
batch 4 5 only.