ECE 558658 VLSI Design Flow

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ECE 558/658VLSI Design Flow
Lecture 2 Sept 10, 2002 Presented by Andy
Laffely alaffely_at_ecs.umass.edu
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Lecture Overview

• TA web page
• Circuit development design flow
• Introduce Microwind with a NOR gate example

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Course Pagewww.ecs.umass.edu/ece/vspgroup/burleso
n/courses/558/TA Pagehttp//vsp2.ecs.umass.edu/v
spg/658/TA_Tools/index.html

• TA information
• Different tools for Grad and Undergrad
• Useful links for
• Models and Tools
• Design rules
• Hand calculation parameters
• Examples!!!!
• ETC

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Goal

• The course will cover basic theory and techniques
  of digital VLSI design in CMOS technology. Topics
  include CMOS devices and circuits, fabrication
  processes, static and dynamic logic structures,
  chip layout, simulation and testing, low power
  techniques, design tools and methodologies, VLSI
  architecture. We use full-custom techniques to
  design basic cells and regular structures such as
  data-path and memory. There is an emphasis on
  modern design issues in interconnect and
  clocking. We will also use several case-studies
  to explore recent real-world VLSI designs (e.g.
  Pentium, Alpha, PowerPC StrongARM, etc.) and
  papers from the recent research literature.
  On-campus students will design small test
  circuits using various CAD tools. Circuits will
  be verified and analyzed for performance with
  various simulators. Some final project designs
  will be fabricated and returned to students the
  following semester for testing. (4 credits)

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Terminology

• CMOS Technology
• Complementary MOS transistor
• Size/process identifies technology
• Layout
• Mask
• Layers Gate, Oxide, Via, Wells, Metal, Poly,
  Active, Diffusion, Channel
• Simulation vs. Verification
• Simulation Model the electrical performance
• Verification Model the switching behavior

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Design Methodology

• Full Custom The designer creates layout masks by
  hand.
• Potentially fastest and most power efficient
  designs
• Long design cycle
• Standard Cell The designer uses high level
  programming language to describe the system and
  lets the computer make the masks.
• Shorter design cycle
• Less efficient designs

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Standard Cell Design

• Architecture Design Specify and test your system
  at the behavioral level
• Layout Synthesis
• Generate a netlist of standard cells
• Software Places and routes the cells
• Layout Verification and Simulation After the
  layout is generated, verify and simulate your
  system

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Full Custom

• Architecture Design Specify and test your system
  at the behavioral level
• Logic Design Develop a schematic of your system
• Verify it meets the behavioral model
• Circuit Design Calculate the approximate size of
  the transistors
• Simulate both the speed and power consumption of
  your design using detailed simulator
• Layout Design Build the mask layers by hand
• Verify the logic
• Simulate the system for performance using

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Architecture Design

• Goal Create a high-level (Behavioral)
  representation of your system
• Tools Verilog, VHDL, System C
• Synthesizable (PLDs and/or ASIC)
• Non-synthesizable
• More in future lectures

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Logic Design and Verification

• Translate system level description into
  transistors
• Many logic styles
• Schematic representation
• Logic verification
• Simplistic models - to verify functionality
• Fast - can run many cases
• 558 - Use DSC2
• 658 - Use Cadence Schematic Verilog or IRSIM

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Circuit Design

• Calculate transistor sizes
• Performance evaluation
• Complex models - to evaluate timing and power
• Slow - run only selected cases
• 558 - Use Microwind
• 658 - Use HSPICE
• Digital Integrated Circuits A Design
  Perspective, J. Rabaey, Prentice-Hall, 1996,
  first edition, ISBN 0-13-178609-1. Web Page for
  the book including Powerpoint and PDF of all
  slides, MAGIC, SPICE, etc. (Important list of
  errors (Errata) in the book) Note that the second
  edition of the textbook will be available in
  October 2002, however this course will use the
  first edition.

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Layout

• Translate schematic to layout
• Need to know the design rules
• Layout representation may not be similar to
  schematic
• Logic verification
• Compare netlists (Layout vs. Schematic, LVS)
• Simulators (DSC2 or Vertuoso-IRSIM)
• Performance evaluation
• Use detailed simulations
• 558 - Use Microwind
• 658 - Use HSPICE