Verilog HDL, Powered by PLI: a Suitable Framework for Describing and Modeling Asynchronous Circuits

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Verilog HDL, Powered by PLI a Suitable Framework
for Describing and Modeling Asynchronous Circuits
at All Levels of Abstraction

• Arash Saifhashemi
• H. Pedram
• Email saif, pedram_at_ce.aut.ac.ir
• Amirkabir University of Technology
• (Tehran Polytechnic)
• Department of Computer Engineering Information
  Technology
• IEEE DAC 40th
• Anaheim, June 2-6, 2003

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Outline
Oh earth! Do not turn without me. Oh Time! Do
not go without me. (Rumi)

• Introduction
• Verilog and PLI
• Channel Abstraction
• Some Extensions
• Selection
• Conclusions

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Introduction

• The CSP Language
• Similar to programming languages, plus new
  features
• Channels Communication Abstraction
• Fine Grained Concurrency
• Selection
• What is the problem with CSP?
• Not standard
• Lower levels of the design?
• Simulators
• Standard HDLs for modeling CSP
• Verilog vs. VHDL
• Verilog Parallel blocks(fork-join)
• VHDL Channel abstraction
• We want both features at the same time!

A B ( C (DE) ) F
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Verilog and PLI

• Using Verilog HDL for modeling CSP
• Fine grained concurrency
• Channels?
• PLI (Programming Language Interface)
• What is PLI?
• An interface to C language
• Like custom system calls
• Almost all aspects of the C language in Verilog
• Key feature shared memory

module Sample_PLI reg 150 a initial Begin
a My_RND_Generator()//PLI     if
(Is_Prime(a)) //PLI My_Display(a is
prime)//PLI end endmodule
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Channel Abstraction

• How to make channels abstract?
• Two goals
• Hide the protocol extra signals
• Hide the handshaking

module producer (out, req, ack) input req outp
ut out, ack reg data always begin //Produce
data wait (req1) ack 1 out
data wait (req 0) ack
0 end endmodule A sample Verilog code of
channels
module producer (out) output out reg data al
ways begin //Produce data //out!data
?? end endmodule The ideal case
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Channel Abstraction

• Hide extra signals in the PLI shared memory

typedef struct t_channel BOOL bWriteDone BOOL
bReadDone char buffer handle
hSimulationNet SChannel PLI Shared Memory
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Channel Abstraction
Channel

• The Outline of the Algorithm

Unfortunately, this code does not work! In PLI we
lose concurrency -gt Deadlock
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Channel Abstraction

• Solution
• Make PLI routines atomic actions -gt no wait
• Send wait actions to Verilog space -gt no deadlock

typedef struct t_channel BOOL bWriteDone
BOOL bIsReadRequest char prtBuffer
handle hReadDone handle hReadClear handle hS
imulationNet SChannel Revised version of the
channel struct in PLI Shared Memory
//produce data out!data
in?data //consume data
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Channel Abstraction
module c(in) ... reg bReadClear always begin b
ReadClear1'b0 RegisterReaderFlag(in,bReadCle
ar) wait(bReadClear1) Read
(in,data) ResetReadRequest(in) //Consume
data end endmodule
module p(out) ... reg bReadDone always begin
//Produce data bReadDone1'b0 Write(out,da
ta) RegisterReadDoneFlag(out,bReadDone) wai
t(bReadDone1'b1) ResetWriteRequest(out) end
endmodule

• First goal is done
• Hiding the handshake signal definitions
• Second goal?
• Hiding the handshaking itself

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Channel Abstraction

• Verilogs built-in preprocessor (Macro)

module p(prt) ... USES_CHANNEL always begin //
Produce data WRITE(out,data) end endmodule
//produce data out!data
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Channel Abstraction

• The final producer-consumer example

module p(prt) ... USES_CHANNEL always begin //
Produce data WRITE(out,data) end endmodule
module c(in) ... USES_CHANNEL always begin
READ(in,data) //consume data end endmodule
//produce data out!data
in?data //consume data
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Channel Abstraction

• Probe Function

typedef struct t_channel BOOL bWriteDone
BOOL bIsReadRequest char prtBuffer
handle hReadDone handle hReadClear ... SCha
nnel
Probe_Calltf(port) if(bIsWriteDone
bIsReadRequest) return TRUE else return
FALSE
//Verilog if (Probe(some_port)) Begin ... end
//Verilog if (PROBE(some_port)) Begin ... end
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Extensions to basic algorithm

• Customizing
• Any handshaking protocol
• Tracking the handshaking phase a PLI global
  variable
• Pure handshaking in CHP
• AB
• HANDSHAKE(A)
• Error checking
• my_PLI_Func(a)
• Type
• Length
• Statistical measurements
• Count the number of communication actions
• Power estimation
• Two directional channels
• One-to-many and many-to-many buses
• Bullet Operator
• A!a? B?b
• WRITE_READ(A,a,B,b)

• Mixed Mode Simulation
• Single Test bench
• Verilog-VHDL

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Another CSP Feature

• Selection
• Wait until there is no true guard
• Only one true guard?
• Execute the following statement
• More than one true guard?
• Arbitration

While (PROBE(A) PROBE(B)) begin STEP_DEL
AY End if (PROBE(A)) WRITE(A,x) if
(PROBE(B)) WRITE(B,x) (Deterministic)
While (PROBE(A) PROBE(B)) begin STEP_DEL
AY end arbNumber Arbitrate(A,B) if (arbNumber
1) WRITE(A, x) if (arbNumber 2)
WRITE(B, x) (Non-Deterministic)
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Conclusions

• Verilog is capable of describing circuits at CSP
  level
• At the same abstraction level of CSP
• Flexible customizable
• Sticking to standards
• Mixed mode simulation is possible
• Since most Asynchronous designers use CSP at the
  behavioral level
• Verilog can be used to describe asynchronous
  circuits at all levels of the design
• A Complete design flow can be built based on
  Verilog