Sequential Logic Circuits

1
Sequential Logic Circuits

• Trac D. Tran
• ECE Department
• The Johns Hopkins University
• Baltimore, MD 21218

2
Outline

• Sequential logic and memory elements
• Set-Reset flip-flop
• Toggle flip-flop or edge-triggered flip-flop
• Sequential circuits as finite state machine
• Applications
• Car Alarm
• Modulo-N binary counter
• Random access memory (RAM)

3
Sequential Logic

• Combinatorial logic circuits current input
  values determine the output value
• Sequential logic circuits output value also
  depends on past input values. Sequential logic
  circuits have memory
• Common memory elements
• Set-Reset Flip-Flop (SR-FF, RS Latch) basic
  computer memory cell
• Toggle Flip-Flop (T-FF) basic computer counting
  cell

4
Set-Reset Flip-Flop
Timing Diagram
S
R
Q
Q
Comment
hold
reset
set
strange state
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SR-FF Analysis
S
R
Q
Q

• Q remembers which input, S or R, was 1 last
• If S then Q1
• If R then Q0

initial state
set transition
reset transition
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Set-Reset Flip-Flop On Hold
Timing Diagram
1
0
S
R
Q
Q
0
1

• Initial state S0, R0, Q0

• What about S0, R0, Q1

• When SR0, Q is on hold (stays put, no change)

7
SR-FF Set Transition
Timing Diagram
0
1
S
0
R
Q
1
Q
0
0

• When S1, Q is set to 1
• What happens when S is back down to 0?

8
SR-FF Reset Transition
Timing Diagram
0
0
S
1
R
Q
0
Q
1
0

• When R1, Q is set to 0
• What happens when R is back down to 0?

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SR-FF A Finite State Machine
S1
Q0 Q1
Q1 Q0
S0,1 R0
S0 R0,1
R1

• Finite state machine
• Circle State
• Arrow State transition
• S,R machine controls, transitional stimuli

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Example Car Alarm
alarm ignited
5V
S
SR-FF
Accelerometer
ALARM
Q
R
alarm off
5V
S
R
Q
alarm on
alarm off
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Toggle Flip-Flop

• Toggle flip-flop (T-FF) is the computers basic
  counting cell
• Inputs
• T toggle
• CLR clear
• Output
• Q
• Operation
• Q toggles (changes) whenever there is a 1-to-0
  transition at the T input
• When CLR1, Q resets to 0 remains there as long
  as CLR does not change

T
T-FF
CLR
Q
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T-FF Timing Diagram
T
T-FF
CLR
Q
T
CLR
Q
Timing Diagram
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Finite State Machine for T-FF
CLR0
T
CLR1
Q0
else
Q1
else
CLR0
T

• Finite state machine for T-FF
• 2 states output Q is either 1 or 0
• State transition whenever T (clock goes down)
  and CLR is not activated

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Application Binary Counter
Q0
Q1
Q2
T
Q
T
Q
T
Q
A
T-FF
T-FF
T-FF
CLR
CLR
CLR
0
0
0
3-bit Modulo-8 Counter
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Counter Finite State Machine
else
010
001
011
000
100
CLR1
111
101
110

• FSM for counter
• n states depends on what we count up to
• State transition whenever clock goes down
• Another transition whenever CLEAR is activated

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More on Mod-N Counter

• How many T-FFs are required to implement a mod-N
  counter?

• What if N is not a power of 2?
• Need to activate CLEAR signal when counter
  reaches N

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Random Access Memory (RAM)

• RAM Random Access Memory
• Critical component of any digital computing
  system
• Each cell is indexed by a unique address. For
  example, for a 64-cell RAM, we need 6-bit
  addresses
• Consider the simple example
• 1-bit RAM cell
• 64 cells total with 6-bit addresses
• Goals
• Write to store DATA (either 0 or 1) in the
  addressed cell
• Read to retrieve DATA from a requested address

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1-bit RAM Cell Address Circuit

• Design a sequential logic circuit to read and/or
  write a single input DATA bit to memory cell
  indexed 30 (64 cells total)

a0
a1
a2
ADDR30a5.a4.a3.a2.a1.a0
a3
a4
a5
Address Recognition Circuit

• ADDR30 is only activated when the address 011110
  is matched

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1-bit RAM Cell Writing Circuit
0
1
0
DATA
S
SR-FF
ADDR30
MEM30
0
1
R
Q
DATA
1
0
0
1
RAM Writing Circuit

• DATA is stored in MEM30 DATAMEM30
• DATA is held in memory when ADDR300

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1-bit RAM Cell Reading Circuit
S
SR-FF
MEM30
R
Q
OUTDATA
ADDR30
RAM Reading Circuit

• Retrieved value OUTDATA is always the same as the
  value stored in the RAM cell MEM30
• Some smart cards contain 1-bit memory
• How about N-bit RAM cell?