Reconfigurable Hardware Testbed for Digital Signal Processing

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Reconfigurable Hardware Testbed for Digital
Signal Processing

• Hayden So
• Prof. R. W. Brodersen
• EECS, UC Berkeley

BWRC Retreat, Jan 2000
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Motivations

• Exploration of next generation communication
  algorithm requires rapid prototyping
• Software simulation is too slow
• Avoid wasting manpower in designing for both
  testbed and final IC implementation

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A 2-fold Design Goal

• top-level input same as IC flow
• Simulink diagram
• co-explore design flow with IC design flow

• A highly configurable hardware
• Full system emulation
• Tradeoff area and power for max. performance
• Comparison between FPGA and DSP
• Speed, Area, other tradeoff...

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FPGA vs. DSP ? Speed

• Speed of FPGA 10x speed of DSP

• Note
• Plots are relative speedup of FPGA implementation
  w.r.t. DSP implementation
• All designs fit on one single chip

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FPGA vs. DSP ? Area

• Size of FPGA limited, but not DSP
• Xilinx XVC1000 can fit 64 16-bits real
  multiplier 16 16-bits complex multipliers?
  32-point FFT, 8x8 matrix-multiply

Floorplan of a 8x8 matrix-multiplier on a XCV1000
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FPGA vs. DSP ? price of parallelism

• Large design ? complex on-chip interconnect ?
  lower clock frequency
• Larger design ? off-chip communication ? even
  slower

• Not enough I/O pins ? I/O bottleneck
• A 8x8 16-bits matrix requires 1024 pins already!
• Compiling (place route) for FPGA takes
  super-exponential time if inappropriate HDL
  design flow is used

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Design Flow ? overview

• Where does testbed flow fit in IC flow?
• Share the same front-end

Simulink MDL File
BCC
Slight modification
The rest of IC flow
The rest of testbed flow
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Design Flow - challenge of the front-end

• Simulink hierarchy not exactly the same as
  implementation
• e.g. a 16 bits adder is different from a 12 bits
  adder on IC, FPGA, but the same for simulink, DSP
• requires exploration of entire hierarchy to
  distinguish two subsystems
• Different targets have differences that are hard
  to generalize by one single program
• e.g. Clocking methodology, which is absence from
  simulink, is different for IC, FPGA and DSP
  implementation
• Output for DSP (C code) is very different from
  FPGA IC (EDIF netlist)

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Conclusion

• FPGA has a clear speed advantage over DSP. But
  multiple-chip implementation is inevitable
• Effect of off-chip communication on performance
  to be determined
• Advantage of exploiting all potential parallelism
  in FPGA comes in a great price
• careful multiple-chip partitioning
• careful place-and-route
• Demand a good design flow for partitioning into
  multiple FPGA chips
• Design flow for DSP is not mature
• requires a much better optimized compiler