A SOFTWARE RECONFIGURABLE ARCHITECTURE FOR 3G AND WIRELESS SYSTEMS

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A SOFTWARE RE-CONFIGURABLE ARCHITECTURE FOR 3G
AND WIRELESS SYSTEMS
Euro Sereni (presenter) Giuseppe Baruffa,
Fabrizio Frescura, Paolo Antognoni
Department of Electronic and Information
Engineering (DIEI) - University of Perugia - Via
G. Duranti 93 06125, Perugia, Italy, email
sereni, baruffa, frescura_at_diei.unipg.it
Digilab 2000 Via A. Vici z.i. La Paciana
06034, Foligno (PG), Italy, email
antognoni_at_digilab2000.it
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Summary

• Mobile and wireless communications scenario
• Software Radio for transceivers a winning choice
• The implementation testbed
• Digital Base Band
• Analog Radio Frequency
• Selection of communication standards
• Conclusions and future work

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Mobile and wireless communications

• Next generation software radio technology will
  provide
• the use of a single terminal
• integrated applications for the different
  standards

• Current generation wireless technology requires
• the use of different terminals
• dedicated applications for each standard

GPRS
UMTS
GPRS
UMTS
802.11/Hiperlan
802.11/Hiperlan
Bluetooth
Bluetooth
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3G and Wireless-LAN scenario.

• WLAN services offer new business opportunities to
  service providers, and a comprehensive solution
  with GPRS and UMTS networks would provide users
  with flexibility and portability.
• The standards currently in the market are GPRS,
  IEEE802.11/b and Bluetooth.
• Third generation standards (UMTS and
  IEEE802.11/a) will provide high data rate radio
  access and they will allow new and more complex
  services.
• From a digital point of view, the complexity of
  re-configurable systems will depend on the
  possibility to implement an appropriate software
  library. The reprogramming ability of the
  hardware platform (i.e. DSP/FPGA) will guarantee
  the system re-configuration.

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Software Radio terminals

• The software radio terminals must be auto
  re-configurable, in order to match the different
  telecommunication standards.
• Software Radio (SWR) defines a radio system
  capable to change its radio parameters by
  software rather than by hardware, such as
• operating frequency range
• bandwidth
• level of power
• type of modulation
• channel coding
• ecc..
• Powerful Digital Signal Processors are needed to
  implement the demanded re-configurability

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Ideal Software Radio system

• Software Radio Transceiver, in its widest
  meaning, defines a general TX/RX architecture
  directly operating on an RF digitized information
  stream, which can be completely reconfigured by
  software.
• The Analog to Digital conversion (ADC) is moved
  as near as possible to the antenna.
• SWR capability to support different standards is
  mainly due to
• The range of frequencies and bandwidth of the RF
  stage
• The greatest bandwidth assigned to a signal
• The sampling frequency of the ADCs
• The maximum dynamic range
• The computational capability of the digital
  processors (DSP in general, and FPGA).

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Receiver Architecture

• Analog processing is limited at the RF front-end
  (pass-band filter LNA)
• The ADC generates a digital RF stream that is fed
  to a RF-BB DSP subsystem that
• Centres the received signal spectrum to the band
  of services of interest
• Lowers the sampling frequency of the digital
  stream down to the required standard rate
• Operates the necessary digital filtering in order
  to reject the unwanted adjacent signals
• Demodulates, channel- and source-decodes the
  symbol flow.
• However, this architecture is unfeasible for
  nowadays technology
• The analog RF stage should operate in a range
  varying from hundreds of MHz to tens of GHz.
• The required precision and sampling rate impose
  severe constraints on the ADC.

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Software Radio Transceiver Architecture

• Nowadays, the technology does not allow having a
  digital RF stage (Digital Front-End), so the SWR
  transceiver uses different analog RF stages, one
  for each considered standard.

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Optimisation issues for 3G and Wireless systems

• The number of bit in the ADC and DAC converters.
• ADCs show an exponential relationship between
  resolution and dissipated power.
• The processing area and power consumption are a
  polynomial function of the number of bits.
• Careful selection is required for power control
  and AGC subsystems.
• The splitting of processing functions between the
  ASIC and the DSP.
• Implementing functions on ASIC, does not always
  help to reduce space and power consumption, since
  different functions correspond to increased ASIC
  area.
• The number of functions performed by the DSP
  should be maximised in order to maintain an high
  degree of flexibility.
• The impact on the radio performance of different
  sub optimal algorithms.
• Any sub optimal algorithm must be carefully
  evaluated with respect to the ideal case, because
  any degradation leads directly to increased power
  requirements for transmission and/or to a reduced
  sensitivity of the receiver

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Activity Plan
Software Radio Transceiver
System Integration
2Q03
GPRS
1Q03
UMTS
RF module
4Q02
IEEE802.11/b
ASIC/ FPGA Module
2 DSP C6416 PCI Board
Bluetooth protocol stack
3Q02
C6416
C6416 PCI Board
IEEE802.11/a
2Q02
ASIC Viterbi Decoder
Commercial RF Integration
1Q02
Software
2 DSPs C6202 PCI board
C6202
Bluetooth module
Hardware
1Q02
2Q02
3Q02
4Q02
1Q03
2Q03
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Baseband Software Radio Hardware Testbed (1/2)

• For the selected systems (IEEE 802.11\a, UMTS,
  GPRS), a PCI hardware testbed has been devised,
  based on two DSPs and one Forward Error
  Correction device.
• This board can provide for high computational
  capability, straightforward utilization and
  trouble-free modularity.
• Main hardware features are
• Two fixed-point 250 MHz TMS320C6202 DSPs (4.000
  MIPS)
• One Reed-Solomon and Viterbi decoder (up to 62
  Mbit/s)
• 1 Mbit,125 MHz, Dual Port SRAM
• 32 Mbit, 125 MHz, SBSRAM
• One PCI Bridge, with 66 MHz 32-Bit PowerPC RISC
  CPU Core
• 128 Mbit external SDRAM
• PCI Daughter board standard expansion connectors.
• Bluetooth external module

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Baseband Software Radio Hardware Testbed (2/2)
Bluetooth Module
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RF Software Radio Hardware Testbed (1/2)

• A dual-band (902-928 MHz or 2.025 2.5 GHz)
  software selectable quadrature modulator, has
  been selected,
• Tx Front-End
• Dual 40 MHz 10-bit DAC converters
• 6-pole Butterworth clock rejection filters
• Low phase-noise frequency synthesizer
  programmable in steps of 100 KHz
• Output power can be controlled using 10-bit
  control words (Non-linear scale)
• Selectable internal/external 10 MHz frequency
  synthesizer
• Rx Front-End
• Sensitivity -56 dBm RF input for full scale
  10-bit output samples
• Built-in AGC, 70 dB dynamic range.
• Low phase-noise frequency synthesizer
  programmable in steps of 100 KHz
• Dual 10-bit ADC, 40 Msample/s
• Two base band filter options, for Narrow-band
  (lt300 KHz) or Wideband (lt20 MHz) applications

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RF Software Radio Hardware Testbed (2/2)
Tx power control
Data I In
I
10-bit DAC
Low-Pass Filter

Data Q In
RF out
Q
10-bit DAC
Low-Pass Filter
Sample clk in
90deg 0deg
frequency selection
Frequency Synthesizer
AGC
RF In
10-bit ADC
Data I out
10-bit ADC
Data Q out
Digital clock out
90deg 0deg
40 Mhz oscillator
frequency selection
Frequency Synthesizer
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Physical layers of IEEE 802.11\a, UMTS, and GPRS,
at the transmitter side (1/2)

• IEEE 802.11\a because of the high throughput of
  this WLAN standard (up to 54 Mbit/s), a dedicated
  unit has to realize OFDM modulation (i.e. an IFFT
  operation) and Viterbi decoding. This is the most
  computationally demanding standard.
• UMTS according to 3GPP, the spreading requires
  an ASIC/FPGA device or a very powerful DSP (such
  as, for example, TMS320C64x), while encoding,
  interleaving and rate matching are carried out by
  a less performing DSP
• GPRS a single DSP unit is sufficient.
  Similarities with GSM are exploitable to
  implement it.

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Physical layers of IEEE 802.11\a, UMTS, and GPRS,
at the transmitter side (2/2)
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IEEE 802.11\a testbed Software Architecture
DSP 1
Puncturing
BPSK QPSK 16-QAM 64-QAM
Bit Interleaving
Convolutional Encoder
Data Input
DSP 2
Pilot carrier Insertion
IFFT
Base Band Output
Tx Side
DSP 2
Rx Side
FFT
Symbol Timing Sync.
Base Band Input
DSP 1
De-Interleaving
Channel Equalization
De- Puncturing
Demapping
Data Output
Viterbi Decoder
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IEEE 802.11a Computational Complexity
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Conclusions

• A modular architecture for implementing mobile
  and wireless communications standards and for
  evaluating their complexity as been introduced.
• The adoption of reconfigurable computing devices
  allows testing several air interfaces simply by
  uploading a new program on the testbed system
• The testbed can be used to study the feasibility
  of future software radio systems
• The results achieved have been considered and
  shown