Pipelining and Hazards

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Pipelining and Hazards

• Vincent H. Berk
• September 30, 2005
• Reading for today Chapter A.1 A.3, article
  PattersonDitzel
• Reading for Monday 3.1, A.4 A.6, article
  Yeager

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Review Pipelined DLX DatapathFigure A.18, Page
A-31
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Hazards

• Hazards are situations that hamper execution flow
• Structural Hazards
• Resource Conflict, hardware cannot support all
  possible combinations of instructions
  simultaneously.
• Data Hazards
• Source operands are not available instruction
  depends on results of previous instructions still
  in the pipeline
• Control Hazards
• Changes in program counter

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Structural Hazards
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One Memory Port/Structural Hazardsfrom SECOND
EDITION
I n s t r. O r d e r
Load
Instr 1
Instr 2
stall
Instr 3
Mem
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Structural Hazard Single Memory
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Speed Up Equation for Pipelining

• Speedup from pipelining
• Ideal CPI CPIunpipelined /Pipeline depth
• Speedup

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Speed Up Equation for Pipelining
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Example Dual-port vs. Single-port

• Machine A Dual ported memory
• Machine B Single ported memory, but its
  pipelined implementation has a clock rate that is
  1.2 times faster
• Ideal CPI1 for both
• Loads and stores are 40 of instructions executed
• Machine A is 1.17 times faster

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Data Hazards

• sub R2, R1, R3 R2 written by sub
• and R12, R2, R5 first operand (R2) depends on
  sub
• or R13, R6, R2 second operand (R2) depends on
  sub
• add R14, R2, R2 both operands depend on sub
• sw 100 (R2), R15 index (R2) depends on sub
• Notice that the value written into R2 by the
  subtract instruction is needed in all of the
  following instructions

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Classification of Data Hazards

• Consider instructions i and j, where i occurs
  before j.
• RAW (read after write) j tries to read a
  source before i writes it, so j gets the old
  value
• WAW (write after write) j tries to write an
  operand before it is written by i (only possible
  in pipelines that write in more than one pipe
  stage or allow an instruction to proceed even
  when a previous instruction is stalled)
• WAR (write after read) j tries to write a
  destination before it is read by i, so i
  incorrectly gets the new value (only possible
  when some instructions can write results early in
  the pipeline and other instructions can read
  sources late in the pipeline)

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Software Solution

• Compiler recognizes data hazard and adds nops to
  eliminate it
• sub R2, R1, R3 register R2 written by sub
• nop no operation
• nop
• nop
• and R12, R2, R5 now, result from sub available
• or R13, R6, R2
• add R14, R2, R2
• sw 100 (R2), R15

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Data Hazard Control Stalls

• Hazard occurs when instruction reads (in ID
  stage) register that will be written by an
  earlier instruction (in WB stage)
• Idea Detect hazard and stall instructions in
  pipeline until hazard is resolved
• Detect hazard by comparing read fields in IF/ID
  pipeline register with write fields in later
  pipeline registers (ID/EX, EX/MEM, MEM/WB)
• To add bubble in pipeline
• Preserve PC register and IF/ID pipeline
  register
• Change EX, MEM, and WB control fields of ID/EX
  pipeline
• register to do nothing

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Data Hazard Reduction Forwarding

• Needed result is available before it is written
  into register file in WB stage
• Idea Use temporary results instead of waiting
  for registers to be written
• Cannot solve problem of write (load) followed by
  read
• Almost all pipelined machines today use some form
  of forwarding

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Data Hazard on R1Figure A.6, Page A-17
I n s t r. O r d e r
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Forwarding to Avoid Data HazardFigure A.7, Page
A-18
CC 1
CC 5
CC 2
CC 3
CC 4
CC 6
I n s t r. O r d e r
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Data Hazard Even with Forwarding Figure A.9,
Page A-20
CC 1
CC 5
CC 2
CC 3
CC 4
I n s t r. O r d e r
IM
Reg
DM
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Data Hazard Even with ForwardingFigure A.10,
Page A-21
CC 1
CC 5
CC 2
CC 3
CC 4
CC 6
lw r1, 0(r2)
I n s t r. O r d e r
sub r4, r1, r5
IM
Reg
and r6, r1, r7
IM
or r8, r1, r9
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(No Transcript)
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Control Hazard on BranchesThree Stage Stall
CC 1
CC 5
CC 2
CC 3
CC 4
CC 6
CC 7
CC 8
CC 9
40 beqz R1, 36
Reg
44 and R12, R2, R5
Program Execution Order (in instructions)
48 or R13, R6, R2
52 add R14, R2, R2
80 ld R4, R7, 100
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(No Transcript)
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Branch Stall Impact

• If CPI 1, 30 branches, 3-cycle stall ? new
  CPI 1.9!
• Two simple solutions
• Predict not taken
• Continue with decoding code that is already in
  Instruction Cache
• Usually lt 50 correct, however, no stalls when
  correct
• Branch delay slot
• The first instruction following the branch is
  ALWAYS executed
• Compiler can figure out what to put there

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Delayed Branch
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Delayed Branch

• Where to get instructions to fill branch delay
  slot?
• Before branch instruction
• From the target address only valuable when
  branch taken
• From fall through only valuable when branch
  not taken
• Canceling branches allow more slots to be
  filled
• Compiler effectiveness for single branch delay
  slot
• Fills about 60 of branch delay slots
• About 80 of instructions executed in branch
  delay slots useful
• in computation
• About 50 (60 x 80) of slots usefully filled

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Evaluating Branch Alternatives