ECE 426 VLSI System Design

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ECE 426 - VLSI System Design

• Lecture 11 - FSM State Coding Timing
• March 5, 2003

Prof. John NestorECE DepartmentLafayette
CollegeEaston, Pennsylvania 18042nestorj_at_lafayet
te.edu
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Announcements

• References
• C. Cummings, State Machine Coding Styles for
  Synthesis, SNUG 1998,
• available at http//www.sunburst-design.com

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Where we are...

• Last Time
• Handshaking
• FIFOs
• Today - Register Transfer Design
• State Coding Assignment
• Timing

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State Assignment

• During design, we use symbolic state names
• Actual state code are determined by state
  assignment
• Structure (and cost and timing) of logic is
  influenced by state assignment
• Types of state assignment
• Binary (chosen by designer)
• One-Hot
• Output-Coded
• Generated by CAD Tool (Synopsys)

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Binary State Assignment

• Just pick arbitrary values for state code
• Default behavior in Verilog synthesis
• parameter 20 S0 3d0, S13d1,
• always _at_(posedge clk)
• cs lt ns
• always _at_(cs or in1 or )
• case (cs)
• S0
• S1
• default
• endcase

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One-Hot State Assignment

• Use one flip-flop for each state
• Tradeoff use more flip-flops, but usually less
  logic
• Popular in FPGAs (why?)
• parameter 40 S0 5b00001, S15b00010,
• always _at_(posedge clk)
• cs lt ns
• always _at_(cs or in1 or )
• case (cs)
• S0
• S1
• default
• endcase

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One-Hot Example Car Alarm
001
010
100
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One Hot Hand Implementation - Car Alarm

• Fill in from board

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One-Hot State Assignment with Zero Idle

• Idea add all zeros as idle state
• parameter 40 S0 5b00000, S15b00001,
• always _at_(posedge clk)
• cs lt ns
• always _at_(cs or in1 or )
• case (cs)
• S0
• S1
• default
• endcase

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Output-Coded State Machine

• Key idea
• Use state flip-flops directly as outputs
• Assign state codes so outputs have appropriate
  value
• Advantages
• Output asserted during state (not delayed like a
  registered output)
• No output logic!

00
10
01
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Larger Output-Coded Example

• 1966 T-Bird Taillights

Example Source J. Wakerly, Digital Design
Principles and Practices, 3rd ed., Prentice-Hall,
2001
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ASM Diagram - T-Bird Taillights
000 000
111 111
001 000
000 100
011 000
000 110
111 000
000 111
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State Assignment w/ Synpopsys

• Just pick arbitrary values for state code
• Default behavior in Verilog synthesis
• parameter 20 // synopsys enum code
• S0 3d0, S13d1, , S73d7
• // synopsys state_vector cs
• reg 20 // synopsys enum code
• cs, ns
• always _at_(posedge clk)
• cs lt ns
• always _at_(cs or in1 or )
• case (cs)
• ...
• endcase

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Synopsys FSM Commands

• Key ideas
• Use a binary encoding that minimizes logic OR
• Use specialized code, but let tool assign codes
• Works with one FSM per module
• dc_shell commands
• (read design)
• compile
• extract
• set_fsm_encoding_style style
• compile

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Review Delay in Static CMOS

• Delay depends on transistor characteristics and
• parasitic loading (RL, CL) and
• transistor characteristics (Rn, Rp)

tr 2.2(RpRL)CL
tf 2.2(RnRL)CL
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Review Delay in Static CMOS

• Parasitics depend on
• Wire Loading (not known exactly before PR)
• Fanout Loading (gate inputs)

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Review Combinational Network Delay

• We know how to find the delay of one gate
• What about a network of connected gates?

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Path Delay in Combinational Networks

• Overall delay of a network is due to
• Connections of gates
• Combination of rising and falling outputs
• Maximum Delay - time between
• Change on a primary input
• Last change on primary output

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Path Delay - Graph Model
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Path Delay - Graph Model

• Model combinational network as a graph
• Nodes correspond to gates
• Edges correspond to connections, weighted by
  delay
• Worst case delay is defined by the critical path
• Longest path (or paths) when summing weights
• Known as the critical path

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False Paths

• Logic gates are not simple nodessome input
  changes dont cause output changes.
• A false path cannot be exercised due to Boolean
  gate conditions.
• False paths cause pessimistic delay estimates.

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Timing Analyzers

• Function compute longest paths in a large
  circuit
• Additional concerns
• Support sequential logic
• Identify (and ignore) false paths
• A timing analyzer is built in to Design Compiler

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Ways to Improve Path Delay

• Restructure Logic
• Flatten large logic network
• Transistor Sizing
• Custom design make transistors bigger
• Standard cell design choose cell with larger
  transistors
• Physical Design
• Placement - try to place modules to minimize wire
  length
• Routing - route "critical nets" first

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Timing in Design Flow - ASIC Design
START
Design Compiler
Synthesize Blocks / Timing Analysis
Timing OK?
N
Y
Place Route / Timing Analysis
Timing OK?
N
Y
DONE
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Path Delay and Synthesis

• Traditional logic synthesis tools control
• Logic structure
• Transistor size (select modules with different
  driver sizes)
• But, they can't directly control physical design
• Problem interconnect dominates in "deep
  submicron"
• Response "Physical Synthesis" tools

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Physical Synthesis

• New tools combine synthesis, physical design
• Goals
• Better performance
• "Timing Closure" - create design with minimal
  iteration
• Reduced design Time
• Example products
• Synopsys - Physical Compiler
• Monterey Design Automation - Dolphin
• Cadence - PKS
• Magma - Blast Fusion

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Review Timing in Sequential Circuits

• Key constraint D must be stable in "window"
  around active edge
• Setup time - tsetup, tsu
• Hold time - thold, th

Latch "Transparent"
thold
tsetup
thold
tsetup
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Timing Requirements inEdge Triggered Clocking
(Setup Time)

• Given maximum propagation delay - tprop(max)
• tclock must be large enough to meet setup times
• Slack time tslack provides a "safety margin"

Combinational Logic
Register Output
Register Input
Adder
tclock gt tprop(max) tsetup tclock tprop(max)
tsetup tslack
Mux
Clock
tprop(max)
tsetup
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Effect of Clock Skewon Setup-Time Requirements

• Clock may not arrive at FF inputs at same time
• Must account for clock skew in timing

Combinational Logic
Register Output
Register Input
Adder
Mux
tclock gt tprop tsetup tskew
d
Clock
tskew
tprop
tsetup
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Timing Requirements inEdge Triggered Clocking
(Hold Time)

• Given minimum propagation delay - tprop(min)
• tprop(min) must be large enough to meet hold
  times
• Worst case shift register (minimal output delay)

tprop(min) gt thold tprop(min) gt thold - tskew
Combinational Logic
Register Output
Register Input
Adder
Mux
Clock
thold
Shift Register
tprop(min)
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Level-Triggered Clocking (Latch-Based)

• "Two-sided" timing constraint
• Tclk gt tcomb tsetup
• TH lt tcomb(min)
• Difficult to satisfy - want to eliminate second
  constraint by removing "transparency"
• Edge-triggered clocking
• Multiple-phase clocking

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Overview Synopsys Design Compiler

• What's under the hood
• Design Library Database (provided by foundry)
• Description of available cells
• Delay model for available cells
• Storage element setup, hold constraints
• Operating condition info
• Timing Analyzer
• Logic optimization commands
• Technology-independent
• Technology dependent (technology mapping)
• Timing optimization commands
• Logic restructuring (e.g., flattening)
• Timing-driven technology mapping

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Overview Synopsys Design Compiler (cont'd)

• Controls - Constraints
• "Design Rule" Constraints
• Transition time
• Fanout load
• Capacitance
• Timing Constraints
• Clock specification
• Input, output constraints
• Overall delay constraints
• False path specification
• Area Constraints
• Maximum Area

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Running the Design Compiler

• design_analyzer
• graphical interface
• graphical display of design
• passes commands to dc_shell through GUI
• dc_shell - text interface
• command-line interface
• scripts used for complex operations
• used with software development tools like "make"
  in large designs
• Industrial view "real designers use dc_shell

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Timing in the Design Compiler

• DC assumes a synchronous, clock-based system
• Derives setup, hold constraints between registers
• User-specified timing constraints on inputs,
  outputs

Comb. Logic (Internal)
Comb. Logic (Output)
Comb. Logic (Input)
D
Q
D
Q
D
Q
D
Q
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Specifying Timing Constraints in DC

• Clock specification
• Period
• Skew (and uncertainty)
• Input constraints
• Output constraints
• Combinational delay constraints
• Special cases
• false paths
• multicycle paths

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Clock specifications in DC

• Basic command create_clock
• defines clock period
• implies timing constraints on all
  register-register paths
• dc_shell command syntax
• create_clock clockname -period clockpd(ns)
• Example define a 10MHz clock called clk
• create_clock clk -period 100
• DC supports multiple clocks
• Timing analyzer computes "common base period
• Least common multiple of all clocks
• Used by timing analyzer for interactions between
  clocks
• Generally, multiple clocks should be avoided if
  possible

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Clock specifications in DC (cont'd)

• Specifying delay (skew) in clock networks
• Using DC estimates set_propagated_clock
• Absolute delay set_clock_latency
• Unknown delay set_clock_uncertainty
• Specifying an external clock - "virtual" clock
• Use when system clock is not present in current
  block, but block inputs, outputs vary relative to
  clock
• Syntax
• create_clock -period clockpd -name clockname
• Example
• create_clock -period 30 -name sys_clk

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Performance-Based Synthesis

• References
• Synopys Online Documentation (SOLD) Manuals
  -access using the "sold" command
• Design Compiler User Guide
• Design Compiler Tutorial
• Design Compiler Reference Manual
• Pran Kurup and Taher Abbasi, Logic Synthesis
  using Sysnopsys, 2nd ed., Kluwer Academic
  Publishers, 1997.

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Coming Up

• More about Timing
• Input Constraints
• Output Constraints