Stato Upgrade 3D ATLAS Genova

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Stato Upgrade / 3DATLAS Genova

• Genova, 15 November 2007
• G. Darbo - INFN / Genova
• 3D Sensors
• FE-I4 chip design
• B-layer SLHC simulation
• Involved in the activities (Nanni, Roberto,
  Vadim)

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B-Layer Workshop
http//indico.cern.ch/conferenceDisplay.py?confId
21107

• B-layer Replacement WS
• Sept. 28-29, 2007
• Workshop numbers
• 1 1/2 days
• 6 Sessions round table
• 56 registered participants

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(No Transcript)
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Genova
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3D Sensors - New Results
Efficiency

• Efficiency studies of 3D sensors with 2006 test
  beam for perpendicular and inclined sensors.
• Time walk (20ns plateau) measurements with
  injected charge for 3D structures and FE settings.

• 0º
• ? 95.90.1

• 10º
• ? 99.60.1

BEAM
Threshold 3200 e Structure 3E
Column shadow
Ref. M.Cristinziani E.Bolle, O.Rohne 3D ATLAS
RD Meeting 27/10/2007
Time walk
Charge overdrive (above threshold) for ?T 20 ns

• 20 gt power

• 40 gt power

?
?
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3D Sensors

• 3D Sensor Proposal Approved by ATLAS CB
• IRST is processing ATLAS compatible 3D sensors
  (p-substrate)
• DRIE machine (to make holes) not available yet at
  IRST - Holes made by Spanish firm
• First prototype (ATLAS compatible) available in 1
  month
• Sensor qualification will be made in Trento, then
  BB at AMS (we may also do at IZM?) -gt BB mask
  made and ready (Genova)
• Next steps BB and perform single chip tests in
  Genova
• Other production at IRST repeat the same mask
  production with new DRIE, two other runs foreseen
  in 2008 (active edge).
• Buy wafers (high resistivity FZ p-type) cost 68
  /wafer, min. 50 wafers.
• Ref (last meeting) http//indico.cern.ch/conferenc
  eDisplay.py?confId21616

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Wafer Order - Topsil
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Front-end Chip - FE-I4

• Laboratories involved Bonn, CPPM, Genova,
  Nikhef, LBNL.
• Very spread collaboration, difficult organize
  common effort.
• Submission planned 12/2008.

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Tentative footprint (not to scale)
64 x 50um
1000um
200um
pads
180
Slow control
8 x 250
Pixel array 64 x 8
Bias generator
pads
pads
Array I/O power
Special LM for home made bump openings
Bandgap ref.
LVDS test
Voltage regulators
500
pads
11.8mm2 40 40 25 25 130 pads
maximum on 100u pitch.
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Genova Contribution to FE-I4

• Genova (Roberto) has responsibility to implement
  the Command Decoder and other logics that was
  previously in the MCC inside the new FE.
• The test prototype will be submitted the 29th of
  January through MOSIS
• Roberto is implementing a part in the prototype
  (slow control and MCC Command Decoder).
• Cost for estimated 12 mm2 is 51 k
• Roberto is currently working on a CERN
  workstation (we do not have licenses for library
  of 0.13 µm)
• Cost of licenses is 2000 /year.
• We have to decide how to continue to work on
  FE-I4 buy a WS in Genova (for high interactive
  work) or buy one (or more) and put in a CERN
  cluster (and share with other Pixel groups like
  Bonn, )

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FE-I4 Test Chip
Cost sharing between Bonn, CPPM, Genova, LBNL,
Nikef (?). Not decided -gt 2008.
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Layout Simulation Method and Software

• DC1 model of ID upgraded pixel.
• Latest xKalmanOO (tracking).
• Private version of b-tagging software with
  secondary vertices and recalibration for
  different trackerprocess configurations
• B-tagging software was not specifically tuned for
  new setup (all track selection cuts were the same
  as for current pixel).

Ref. V. Kostyukhin, P. Nevski, A. Rozanov
Results presented for upgraded pixel with added
layer (4L) and with modified single b-layer
together with results obtained with current
pixel detector (3L).
Modified layout with single b-layer
Layout with 4-layers L4
Rb1 37.0 mmRb2 absentR1 88.5 mmR2
122.5 mm
Rb1 37.0mm, 1.2 X0 Rb2 50.5mm , 2.2 X0 R1
88.5mmR2 122.5mm
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B-tagging Results
Ref. V. Kostyukhin
Preliminary!!!
WH(120)?uu(bb), no pileup, ATLFAST jets,
reconstructed primary vertex.

• Tracking performance seems ok for 4 layers case
  but b-tagging is worse comparing with current
  design. Track part of b-tagging is mainly
  responsible for worsening.
• Layout with new single b-layer at R37mm and
  removed current b-layer gives significantly
  better performance with existing tracking
  software.
• Single b-layer at R37mm provides some increase
  of b-tagging rejection at high ? region weak
  point of existing pixel detector.

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Simulation

• Vadim (together with Sasha and Pavel Nevski) is
  working on physiscs simulation of the future
  layout of the B-layer Replacement and SLHC Pixel
  detector.
• Next goal are updated results for Valencia WS
  (Dec 2007)
• Liaison with Bonn to work together in the
  Architecture simulation of the FE-I4.
• Try to adapt SimPix for the future FE-I4 (mainly
  Bonn, not .
• Provide