Direct Memory Access DMA

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Direct Memory Access(DMA)

• Anselmo Lastra

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Thursday

• Review
• Cover all semester topics

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Direct Memory Access (DMA)

• Programmed I/O is when CPU reads/writes every
  word
• Problem overhead is high nothing else getting
  done on CPU
• Especially for mass-storage devices like disk
• DMA Let device controller read/write directly
  to memory

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Procedure

• DMA device takes over main bus
• Becomes bus master
• Asserts addresses
• Basically interfaces to memory or memory
  controller

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How?

• DMA device requests bus (assert BR)
• CPU grants request (assert BG)
• CPU takes its signals to Hi-Z

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Transfers

• Continuous DMA controller transfers all data
  (say a disk sector) at once
• As many memory cycles as data
• Burst DMA controller cycle steals, takes a
  cycle at end of every CPU instruction

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End of DMA

• Controller needs to inform CPU
• De-assert BR
• Then CPU lowers BG and proceeds

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DMA Controller

• Needs typical I/O signals
• Interrupt request
• Status of device
• Also needs controls for DMA transfer
• Memory address
• Word count

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Block Diagram
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Typical Driver Interface

• Set the memory address
• Set word count
• Assert GO (usually bit in control word)
• DMA controller requests interrupt when transfer
  complete

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I/O Processors

• Some machines have even more complex controllers
• I/O processors can be programmable
• Now embedded processors are in many I/O devices