TimingOriented Test Generation

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Timing-Oriented Test Generation
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Outline

• Timing requirements
• Classification, conversion, and update
• Propagation - timing calculation v.s. timing
  implication
• Speedup the search process
• Static logic implication
• Pre-characterized timing propagation
• Locations for logic value assignments
• Justification sequence
• Search scheme
• Handle new search problems
• Distinghish sources of ambiguous ranges
• Three-pattern test

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Timing RequirementsClassification, Conversion,
and Update

• Classification
• Largest (smallest)
• RF Relative to (greater/smaller than) a fixed
  value
• RV Relative to a variable value
• Alignment
• Conversion All three others can be converted to
  RF
• Update
• Revise timing requirements when logic/timing
  values of a line changes

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Propagation of Timing Requirements Timing
Calculation v.s. Implication
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Speedup the Search Process Pre-characterized
Timing Propagation

• Static timing analysis result

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Speedup the Search Process Pre-characterized
Timing Propagation

• Timing propagation of falling transition at line
  6
• Falling at line 10 can be justified by falling at
  line 6 only if (31, 33) intersect with the
  required time range at 10

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Speedup the Search Process Logic Value
Assignments

• Primary Inputs v.s. Internal Nodes
• At primary inputs (PIs)
• do not need justification
• may not be the best in term of size of search
  space
• At internal nodes
• main problem can not a priori guarantee that
  these assignments can be justified especially
  timing
• The likehood of success is increased by utilizing
  proposed pre-characterized timing propagation
• Main issue in search process reduce the time to
  traverse through the whole space when no solution
  exists

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Speedup the Search Process Logic Value
Assignments

• Possible Good Locations
• PIs no justification (used by PODEM)
• Head lines logic justification back to PIs are
  trivial (used by FAN)
• High fanout stems easy to induce contradiction
  and reduce search effort
• Places good only for one logic value
• Outputs of high-fanin gates
• Non-controlled response is hard to be justified
• Lines with large P(0) P(1)
• P(0) the probability for the line to be 0
• One logic value is hard to be justified

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Speedup the Search Process Search Scheme

• Search Find a test that satisfies all excitation
  and propagation conditions.
• Path-oriented approach for satisfy propagation
  conditions
• Select a path
• Set the logic conditions to propagate the desired
  transition along the path, and check if a test
  exists
• If no test exists, repeat the same steps until
  all possible propagation paths are enumerated
• Problem When the number of possible propagation
  paths is large but difficult to satisfy most of
  them, path-oriented approach is inefficient
• Proposed solution Traverse entire search space
  only once to find the test that excites the worst
  case delay
• Problem how to search efficiently

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Handling New Search Problems Distinguish Sources
of Ambiguous Ranges

• Causes of ambiguous timing ranges
• Unspecified input values
• Ambiguous delay models
• E.g. ambiguity due to unknown initial value and
  process variation
• Hazard
• Ambiguity caused by delay models can not be
  removed by further specifying input values.
• ATPG has to recognize such ambiguous timing
  ranges and prevent further specification

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Timing-Oriented Test Generation Test Generation
Problems

• Path delay test
• Propagate a transition along the path
• Excite the worst case delay
• Worst case delay excitation
• How robust a test exciting worst-delay can be
• Compare the delay value to STA result
• Compare run time and results on pin-to-pin delay
  and simultaneous delay
• Robust test with high quality (long nominal path
  delay)
• How much delay a robust test can excite, compared
  to the worst excitable delay

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Summary

• We classify and process timing conditions for use
  in timing-oriented ATPG
• We propose new improvements for accelerating
  timing-oriented ATPG
• We identify two new search problems

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List of Publications

• "TA-PSV - Timing Analysis for Partially Specified
  Vectors", will appear in Journal of Electronic
  Testing.
• "Crosstalk test generation for pseudo Intel
  circuits a case study", will appear in
  International Test Conference, Nov 2001.
• "A new gate delay model for simultaneous
  switching and its applications", Design
  Automation Conference, June 2001, pp. 289-294.
• "A new framework for static timing analysis,
  incremental timing analysis, and timing
  simulation", Asian Test Symposium, December 2000,
  pp.102 -107.
• "Incremental timing analysis - Intuition and
  Implementation", SRC TECHCON, September 2000.
• "High quality robust tests for path delay
  faults", IEEE VLSI Test Symposium, April 1997,
  pp.88-93.

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Following pages are hyper linked pages for
Timing-Oriented Test Generation
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Types of Timing Requirements

• Absolute
• Largest (smallest)
• Example Worst case delay excitation
• Relative
• RF Relative to (greater/smaller than) a fixed
  value
• Example To observe a violation, output
  transition needs to arrive later than sample time.

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Types of Timing Requirements (Cont.)

• Relative (Cont.)
• RV Relative to a variable value
• Example To propagate timing of falling
  transition from X to Z, if Y also has a falling
  transition, need AYF ? AXF ?.
• Alignment
• Example To excite crosstalk effects, skew
  between victim line transition and affecting line
  transition should be small.

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Timing Requirements - ConversionsAbsolute to RF
(Exampled by Worst Delay Excitation)

• Static timing analysis (STA) provides min-max
  timing ranges for each circuit output.
• Use the maximal delay obtained from STA as the
  output required time on the associated output to
  convert the timing requirement to RF (relative to
  a fixed value).
• If this required time can not be satisfied, then
  the optimization problem is converted to a series
  of satisfaction problems.

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Timing Requirements - ConversionsRV to RF
RV condition AXR ? AYR
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Timing Requirements - ConversionsAlignment to RF

• Convert alignment to two RV conditions.

QAF,S AVR,S - ? QAF,L AVR,L ?
? RV conditions can be converted to RF conditions.
Timing Requirements - Update
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Timing RequirementsUpdate
End Timing Requirements - Update
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Propagation of Timing Requirements

• Propagation of timing requirements
• Timing calculation
• Treat both necessary and alternative assignments
  as alternative
• Suitable for PODEM based ATPGs
• Formula for forward and backward timing
  calculation have been shown in our previous
  research
• Timing implication
• Perform only necessary assignments
• Good for reducing search space
• Forward propagation is the same as that in timing
  calculation
• We develop new backward timing implications

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Value AssignmentNecessary v.s. Alternative

• How they affect decision tree in test generation
• To reduce fruitless search, D-algorithm and FAN
  perform all observable necessary assignment
  before performing any arbitrary assignment.
• PODEM does not distinguish between necessary and
  alternative assignments (treat both as
  alternative).

End Timing Calculation
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Logic/Timing Backward Implications

• Logic implies logic
• Traditional logic implications
• Timing implies timing
• Timing implies logic
• Backward timing implication may imply logic
  constraints on gate inputs.
• When only one input possibly satisfy given timing
  requirement, this input is required to have a
  transition.
• When certain logic value on gate inputs will
  cause timing violation, these logic values are
  excluded at these inputs.
• Logic implies timing

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Timing Backward ImplicationsTiming Implies Timing

• The calculation of required time is the same as
  those in timing calculation.
• QXR,S (QYR,S) needs to be enforced on either X or
  Y.
• QXR,L (QYR,L) needs to be enforced on both X and
  Y.
• Computation of QXF,S (QYF,S) and QXF,L (QYF,L)
  are dual of above items.

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Timing Backward ImplicationsDominating Inputs

• Dominating input of NAND Z (with input X1 , X2 ,
  ... Xn) the gate input Xj that the transition on
  Xj minimizes (maximizes) (AXjtr dZ,Xjtr) for
  j ? 1, 2, ... n when tr is a to-controlling
  (to-non-controlling) response.

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Timing Backward ImplicationsTiming Implies Logic

• Necessary assignment (when output has a
  to-non-ctrl transition)

More Timing Backward Implication
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Logic/Timing Backward ImplicationsLogic Implies
Timing

• When a pulse with timing violation is desired at
  output, it will impose logic/timing constraints
  on gate inputs.

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Timing Backward ImplicationsTiming Implies Logic
(Cont.)

• Necessary assignment when output has a
  to-non-ctrl transition
• When the transition at a line will certainly
  cause the output response violates the required
  time, then this line should not have the
  corresponding transition.

End Timing Backward Implication
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Pre-characterized Timing PropagationConsider
Simultaneous Delay

• Dominating input of NAND Z (with input X1 , X2 ,
  ... Xn) the gate input Xj that the transition on
  Xj minimizes (maximizes) (AXjtr dZ,Xjtr) for
  j ? 1, 2, ... n when tr is a to-controlling
  (to-non-controlling) response.
• Apply only part of side-input timing ranges that
  keep on-path transitions as dominating
  transitions.
• Timing propagation of non-dominating inputs will
  be blocked.

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Speedup the Search Process Static Logic
Implication

• Static indirect backward implication
• Contrapositive
• Proposed in SOCRATES by Schulz et al.(TCAD 88)
• (P ?Q) ? (Q ?P)
• Redundant identification
• If P 1 can not be justified, then P 0

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Speedup the Search Process Justification Sequence

• When an internal node is set to a value
  inconsistent with its input nodes, it needs to be
  justified.
• Types of justifications
• One/two frame logic justification
• Justification of timing conditions
• Rules for deciding justification sequence
• Nodes close to PIs first help reduce timing
  ranges and reduce the number of candidates for
  timing justification
• Hard-to-justify nodes first help find
  contradiction early

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Handling New Search Problems Three-pattern Tests

• Pre-initialization captures the difference on
  delay due to the charging/discharging of internal
  capacitances
• Pre-initialization values is needed only when
• Two-pattern vectors can not be further refined to
  get a tighter range, and
• Setting the pre-initialization values will help
  refine the output timing range

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Test Generation

• Need to excite and propagate test conditions
  during test generation.
• Need a search algorithm (represents search as a
  decision tree) to find a test that satisfies
  given conditions.
• Search algorithms D-algorithm, PODEM, and FAN.