8 Bit Gray Code Converter

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8 Bit Gray Code Converter

• Rasha Shaba
• Hala Shaba
• Kai Homidi
• Advisor David Parent
• DATE 12/06/04

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Agenda

• Abstract
• Introduction
• Why
• Simple Theory
• Back Ground information
• Project (Experimental) Details
• Verifications of Results
• Lessons Learned
• Summary

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Abstract

• We designed an 8-bit gray code converter
  according to the following specifications.
• Frequency 200 MHz.
• Power lt25mW
• Area lt800mmx800mm

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Introduction

• We chose a gray code converter for our project
  because
• It is applied in a broad range of applications
• It incorporates all principles taught in
  
• EE-166
• The basic theory of our project is to convert a
  series of binary numbers to gray code numbers
  with the use of XOR gates

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The Gray Code

• Natural Binary Gray Code
• 0 0000 0000
• 1 0001 0001
• 2 0010 0011
• 3 0011 0010

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Project Details

• The Gray Code Converter consists of the
  following
• NAND gates
• XOR gates
• D Flip Flops

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NAND Gate
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NAND
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XOR Gate
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XOR
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XOR
XOR
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DFF
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DFF
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Longest Path Calculations
Note All widths are in microns and capacitances
in fF
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Gray Code Converter Schematic
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Gray Code Converter Layout
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Verification (LVS)
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Input Data
Output Data
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Verification of Specifications

• Frequency 200 MHz
• Power 5mW
• Area 178mmx555mm
• Logic Functional

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Lessons Learned

• Advice to EE-166 students
• Start early
• Consult with Professor Parent in office hours
• Pay attention to lecture
• Think of the project as a learning experience
• Advice to EE-166 professors
• Narrow down class notes to more useful examples

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Summary

• The gray code converter project was worthwhile
  because it firmly illustrated the principles
  taught in EE-166 course
• The main results of the project are the following
  
• Timing specifications were met
• The basic principles of design and layout of
  CMOS technology were learned
• Gray code converters will continue to be a main
  components in may systems to come

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Acknowledgements

• Thanks to Hala, Kai, Rasha for putting up with
  us.
• Thanks to Cadence Design Systems for the VLSI lab
• Thanks to Synopsys for Software donation
• Professor David Parent