System Programming System Software, pp'2128'

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System ProgrammingSystem Software, pp.21-28.

• Chia-Hui Chang, Assistant Professor
• Dept. of Computer Science Information
  Engineering
• National Central University, Taiwan

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Traditional (CISC) Machines

• Complex Instruction Set Computers (CISC)
• complicated instruction set
• different instruction formats and lengths
• many different addressing modes
• e.g. VAX or PDP-11 from DEC
• e.g. Intel x86 family
• Reduced Instruction Set Computer (RISC)

3
VAX Architecture (1/6)

• Virtual Address EXtension
• Memory
• All addresses are byte address
• word (2bytes), longword (4bytes),
• quadworad (8bytes), octaword (16bytes)
• All VAX programs operate in a virtual address
  space of 232 bytes
• One half is used for system space
• The other half is called process space, and is
  defined for each program

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VAX Architecture (2/6)

• Registers
• 16 general purpose registers R0R15
• each register is 32-bit long
• R15 (PC) Program Counter
• R14 (SP) Stack Pointer
• R13 (FP) Frame Pointer
• R12 (AP) Argument Pointer
• R6R11 general
• R0R5 are used by some instructions
• PSL process status longword

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VAX Architecture (3/6)

• Data Formats
• Integers byte, word, longword, quadword, or
  octaword
• Negative integers 2s complement representation
• Floating-point 416bytes
• packed decimal (Cpositive, Dnegative,
  Funsigned)
• zoned decimal (digits are represented with ASCII
  codes)
• e.g. 53842, 53842C (packed), 35333834C2 (zoned)
• e.g. -6071, 6071D(packed), 363037D1
• numeric format trailing numeric, leading
  separate numeric

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VAX Architecture (4/6)

• Instruction Formats
• variable -length instruction format
• Addressing Modes
• register mode
• register deferred mode
• autoincrement and autodecrement modes
• several base relative addressing modes
• program-counter relative modes
• indirect addressing mode (called deferred modes)
• immediate operands

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VAX Architecture (5/6)

• Instruction Set
• Goal symmetric with respect to data type
• The instruction mnemonics are formed by
• a prefix that specifies the type of operation
• a suffix that specifies the data type of the
  operands
• a modifier that gives the number of operands
  involved
• e.g. ADDW2, MULL3, CVTWL
• A single instruction for
• saves a designated set of registers
• passes a list of arguments to the procedure
• maintains the stack, frame, and argument pointers
• sets a mask to enable error traps for arithmetic
  operations

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VAX Architecture (6/6)

• Input and Output
• I/O device controllers
• Each controller has a set of control/status and
  data registers, which are assigned locations in
  the physical address space (called I/O space)
• No special instructions are required to access
  registers in I/O space
• The association of an address in I/O space with a
  physical register in a device controller is
  handled by the memory management routines

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Pentium Pro Architecture (1/5)

• Memory
• physical level byte addresses, word, doubleword
• logical level segments and offsets
• In some cases, a segment can also be divided into
  pages
• The segment/offset address specified by the
  programmer is translated into a physical address
  by the x86 MMU (Memory Management Unit)

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Pentium Pro Architecture (2/5)

• Registers
• General-purpose registers
• EAX, EBX, ECX, EDX data manipulation
• ESI, EDI, EBP, ESP address
• Special-purpose registers
• EIP next instruction
• FLAGS status word
• CS code segment register
• SS stack segment register
• DS, ES, FS, and GS data segments
• Floating-point unit (FPU)
• Registers reserved for system programs

16-bit segment registers
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Pentium Pro Architecture (3/5)

• Data Formats
• Integers
• 8-, 16-, 32-bit binary numbers
• negative values 2s complement
• FPU can also handle 64-bit signed integers
• The least significant part of a numeric value is
  stored at the lowest-numbered address
  (little-endian)
• binary coded decimal (BCD)
• unpacked 0000____0000____0000____...0000____
• packed ________________________..______
  __
• Floating-point data formats
• single-precision 32 bits247-bit exponentsign
  bit
• double-precision 64 bits5310-bit exponentsign
  bit
• extended-precision 80 bits6415-bit
  exponentsign bit

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Pentium Pro Architecture (4/5)

• Instruction Formats
• prefix (optional) containing flags that modify
  the operation of instruction
• specify repetition count, segment register, etc.
• opcode (1 or 2 bytes)
• operands and addressing modes
• Addressing Modes
• TA(base register)(index register)(scale
  factor)displacement
• base register any general-purpose registers
• index register any general-purpose registers
  except ESP
• scale factor 1, 2, 4, 8
• displacement 8-, 16-, 32- bit value
• eight addressing modes

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Pentium Pro Architecture (5/5)

• Instruction Set
• 400 different machine instructions
• R-to-R instructions, R-to-M instructions, M-to-M
  instructions
• immediate values,
• special purpose instructions for high-level
  programming language
• entering and leaving procedures,
• checking subscript values against the bounds of
  an array
• Input and Output
• Input is performed by instructions that transfer
  one byte, word, or doubleword from an I/O
  register EAX
• Repetition prefixes allow these instructions to
  transfer an entire string in a single operation