Analog Design Flow

1
Analog Design Flow
Analog/Mixed-Signal System Level Abstraction
LNA
BPF
BPF
LNA
ADC
VCO
Chip Implementation
Circuit Level Description And Optimization
2
Analog Layout

• Transition from Schematic to Layout
• Time-consuming
• - Analog layout is currently done manually.
• Tedious
• - Signals are very sensitive to parasitics.
• - Precise path symmetry is a necessity.
• Usually requires redesign for each new process
• - Analog schematics typically change with
  process
• therefore layout changes as well.

Automate!!!
3
Current Layout Options

• Cadences Virtuoso XL
• Layout of devices is done based on schematic
• - Reliability of auto placement and routing is
  questionable
• Parameterized-Cells (P-Cells)
• Routing is tightly controlled
• - Scalability and robustness are questionable
• Neolinears Neocell
• Neolinear has partnered with Cadence and
  Cadence will support Neocell
• - Neocell is not yet available to be evaluated

4
Virtuoso XL
Devices and pins are placed according to
schematic.
5
Parameterized Cells
Parameterized cells allow devices to be changed
based on width, length, resistance, etc.
W2.0µm L0.25µm M10
NMOS P-Cell
Capacitor P-Cell
C600fF
6
Analog Parameterized Cells
Analog layout consists of the following building
blocks which can be made into p-cells

• Multi-finger Transistors

• Cascoded Transistors

7
Analog Parameterized Cells

• Common Centroided
• Transistors

• Multiple Unit-Cell
• Passive Devices

8
New Layout Options

• Combine Virtuoso XL with the new Analog
  Parameterized Cells.
• New p-cells provide much of the complicated
  routing, relaxing the constraints on the
  auto-router.
• - Auto placement and routing is still
  questionable.
• Create Super P-Cells representing individual
  analog blocks, such as OTAs, comparators, etc.
• Routing is part of the p-cell, therefore it
  is tightly controlled.
• - Library of analog component Super P-Cells must
  be created.

9
Virtuoso XL New P-Cells