Chapter 4 Topics

1
Chapter 4 Topics

• The Design Process
• A 1-bus Microarchitecture for SRC
• Data Path Implementation
• Logic Design for the 1-bus SRC
• The Control Unit
• The 2- and 3-bus Processor Designs
• The Machine Reset Process
• Machine Exceptions

2
Abstract and Concrete Register Transfer
Descriptions

• The abstract RTN for SRC in Chapter 2 defines
  what, not how
• A concrete RTN uses a specific set of real
  registers and buses to accomplish the effect of
  an abstract RTN statement
• Several concrete RTNs could implement the same ISA

3
A Note on the Design Process

• In this chapter presents several SRC designs
• We started in Chap. 2 with an informal
  description
• In this chapter we will propose several block
  diagram architectures to support the abstract
  RTN, then we will
• Write concrete RTN steps consistent with the
  architecture
• Keep track of demands made by concrete RTN on the
  hardware
• Design data path hardware and identify needed
  control signals
• Design a control unit to generate control signals

4
Fig. 4.1 Block Diagram of 1-bus SRC
5
Fig. 4.2 High-Level View of the 1-Bus SRC Design
ADD SUB AND OR SHR SHRA SHL SHC NOT NEG CB INC4
6
Constraints Imposed by the Microarchitecture

• One bus connecting most registers allows many
  different RTs, but only one at a time
• Memory address must be copied into MA by CPU
• Memory data written from or read into MD
• First ALU operand always in A, result goes to C
• Second ALU operand always comes from bus
• Information only goes into IR and MA from bus
• A decoder (not shown) interprets contents of IR
• MA supplies address to memory, not to CPU bus

7
Abstract and Concrete RTN for SRC add Instruction
Abstract RTN (IR ? MPC PC ??PC 4
instruction_execution) instruction_execution
( add ( op 12) ? Rra ??Rrb
Rrc

• Parts of 2 RTs (IR ? MPC PC ??PC 4) done in
  T0
• Single add RT takes 3 concrete RTs (T3, T4, T5)

8
Concrete RTN Gives Information about Sub-units

• The ALU must be able to add two 32-bit values
• ALU must also be able to increment B input by 4
• Memory read must use address from MA and return
  data to MD
• Two RTs separated by in the concrete RTN, as in
  T0 and T1, are operations at the same clock
• Steps T0, T1, and T2 constitute instruction
  fetch, and will be the same for all instructions
• With this implementation, fetch and execute of
  the add instruction takes 6 clock cycles

9
Concrete RTN for Arithmetic Instructions addi
Abstract RTN
addi ( op 13) ? Rra ? Rrb c2?16..0? 2's
comp. sign extend
Tbl 4.2 Concrete RTN for addi
Step RTN T0. MA ???PC C ??PC 4 T1. MD
???MMA PC ?? C T2. IR ??MD T3. A
??Rrb T4. C ??A c2?16..0? sign
ext. T5. Rra ??C

• Differs from add only in step T4
• Establishes requirement for sign extend hardware

10
Fig. 4.3 More Complete view of Registers and
Buses in 1-bus SRC DesignIncluding Some Control
Signals

• Concrete RTN lets us add detail to the data path
• Instruction register logic new paths
• Condition bit flip-flop
• Shift count register

Keep this slide in mind as we discuss concrete
RTN of instructions.
11
Abstract and Concrete RTN for Load and Store
ld ( op 1) ? Rra ? Mdisp st ( op 3)
? Mdisp ? Rra where disp?31..0? ((rb0)
? c2?16..0? sign ext. (rb?0) ? Rrb
c2?16..0? sign extend, 2's comp. )
Tbl 4.3
Step RTN for ld RTN for
st T0-T2 Instruction fetch T3. A ???(rb0 ? 0
rb?0 ? Rrb) T4. C ??A (16_at_IR?16?IR?15..0?)
T5. MA ??C T6. MD ??MMA MD
??Rra T7. Rra ??MD MMA ??MD
12
Notes for Load and Store RTN

• Steps T0 through T2 are the same as for add and
  addi, and for all instructions
• In addition, steps T3 through T5 are the same for
  ld and st, because they calculate disp
• A way is needed to use 0 for Rrb when rb0
• 15 bit sign extension is needed for IR?16..0?
• Memory read into MD occurs at T6 of ld
• Write of MD into memory occurs at T7 of st

13
Concrete RTN for Conditional Branch
br ( op 8) ? (cond ? PC ? Rrb) cond (
c3?2..0?0 ? 0 never c3?2..0?1 ?
1 always c3?2..0?2 ? Rrc0 if register
is zero c3?2..0?3 ? Rrc?0 if register is
nonzero c3?2..0?4 ? Rrc?31?0 if positive or
zero c3?2..0?5 ? Rrc?31?1 ) if negative
Tbl 4.4
Step Concrete RTN T0-T2 Instruction fetch T3. CON
? cond(Rrc) T4. CON ? PC ? Rrb
14
Notes on Conditional Branch RTN

• c3?2..0??are just the low order 3 bits of IR
• cond() is evaluated by a combinational logic
  circuit having inputs from Rrc and c3?2..0?
• The one bit register CON is not accessible to the
  programmer and only holds the output of the
  combinational logic for the condition
• If the branch succeeds, the program counter is
  replaced by the contents of a general reg.

15
Abstract and Concrete RTN for SRC Shift Right
shr ( op 26) ? Rra?31..0? ? (n _at_ 0)
Rrb?31..n? n ( (c3?4..0?0) ? Rrc?4..0?
shift count in reg. (c3?4..0??0) ? c3?4..0?
) or const. field
16
Notes on SRC Shift RTN

• In the abstract RTN, n is defined with
• In the concrete RTN, it is a physical register
• n not only holds the shift count but is used as a
  counter in step T6
• Step T6 is repeated n times as shown by the
  recursion in the RTN
• The control for such repeated steps will be
  treated later

17
Data Path/Control Unit Separation

• Interface between data path and control consists
  of gate and strobe signals
• A gate selects one of several values to apply to
  a common point, say a bus
• A strobe changes the values of the flip-flops in
  a register to match new inputs
• The type of flip-flop used in regs. has much
  influence on control and some on data path
• Latch simpler hardware, but more complex timing
• Edge triggering simpler timing, but about 2?
  hardware

18
Reminder on Latch and Edge-Triggered Operation

• Latch output follows input while strobe is high

D
D
Q
C
C
Q

• Edge triggering samples input at edge time

D
D
Q
C
C
Q
19
Fig. 4.4 The SRC Register File and Its Control
Signals

• Rout gates selected reg. onto bus
• Rin strobed selected reg. from bus
• BAout differs from Rout by gating 0 when R0 is
  selected

BA Base Address
20
Fig. 4.5 Extracting c1, c2, and op from the
Instruction Register

• I?21? is the sign bit of C1 that must be extended
• I?16? is the sign bit of C2 that must be extended
• Sign bits are fanned out from one to several bits
  and gated to bus

21
Fig. 4.6 CPU to Memory Interface MA and MD
Registers

• MD is loaded from memory bus or from CPU bus
• MD can drive CPU bus or memory bus

22
Fig. 4.7 The ALU and Its Associated Registers
23
Figure 4.8. A Logic-Level Design for One Bit of
the 1-Bus SRC ALU
24
From Concrete RTN to Control Signals The Control
Sequence
Tbl 4.6The Instruction Fetch
Step Concrete RTN Control Sequence T0. MA ? PC
C ? PC4 PCout, MAin, Inc4, Cin T1. MD ? MMA
PC ? C Read, Cout, PCin, Wait T2. IR ?
MD MDout, IRin T3. Instruction_execution

• The register transfers are the concrete RTN
• The control signals that cause the register
  transfers make up the control sequence
• Wait prevents the control from advancing to step
  T3 until the memory asserts Done

25
Control Steps, Control Signals, and Timing

• Within a given time step, the order in which
  control signals are written is irrelevant
• In step T0, Cin, Inc4, MAin, PCout PCout,
  MAin, Inc4, Cin
• The only timing distinction within a step is
  between gates and strobes
• The memory read should be started as early as
  possible to reduce the wait
• MA must have the right value before being used
  for the read
• Depending on memory timing, Read could be in T0

26
Control Sequence for the SRC add Instruction
add ( op 12) ? Rra ??Rrb Rrc
Tbl 4.7 The Add Instruction
Step Concrete RTN Control Sequence T0. MA ? PC
C ? PC4 PCout, MAin, Inc4, Cin, Read T1. MD ?
MMA PC ? C Cout, PCin, Wait T2. IR ?
MD MDout, IRin T3. A ? Rrb Grb, Rout,
Ain T4. C ? A Rrc Grc, Rout, ADD,
Cin T5. Rra ? C Cout, Gra, Rin, End

• Note the use of Gra, Grb, Grc to gate the
  correct 5 bit register select code to the regs.
• End signals the control to start over at step T0

27
Control Sequence for the SRC addi Instruction
addi ( op 13) ? Rra ? Rrb c2?16..0? 2's
comp., sign ext.
Tbl 4.8 The addi Instruction
Step Concrete RTN Control Sequence T0. MA ?
PC C ? PC 4 PCout, MAin, Inc4, Cin,
Read T1. MD ? MMA PC ? C Cout, PCin,
Wait T2. IR ? MD MDout, IRin T3. A ?
Rrb Grb, Rout, Ain T4. C ? A c2?16..0?
sign ext. c2out, ADD, Cin T5. Rra ?
C Cout, Gra, Rin, End

• The c2out signal sign extends IR?16..0? and gates
  it to the bus

28
Control Sequence for the SRC st Instruction
st ( op 3) ? Mdisp ? Rra disp?31..0?
((rb0) ? c2?16..0? sign ext. (rb?0) ? Rrb
c2?16..0? sign extend, 2's comp. )
The st Instruction

• Note BAout in T3 compared to Rout in T3 of addi

29
Fig. 4.9 The Shift Counter

• The concrete RTN for shr relies upon a 5 bit
  register to hold the shift count
• It must load, decrement, and have an 0 test

30
Tbl 4.10 Control Sequence for the SRC shr
InstructionLooping
Step Concrete RTN Control Sequence T0-T2 Instruc
tion fetch Instruction fetch T3. n ?
IR?4..0? c1out, Ld T4. (n0) ? (n ?
Rrc?4..0?) n0 ? (Grc, Rout, Ld) T5. C ?
Rrb Grb, Rout, CB, Cin T6. Shr ( (n?0) ?
n?0 ? (Cout, SHR, Cin, (C?31..0? ?
0C?31..1? Decr, Goto6) n ? n-1 Shr)
) T7. Rra ? C Cout, Gra, Rin, End

• Conditional control signals and repeating a
  control step are new concepts

31
Branching
cond ( c3?2..0?0 ? 0 c3?2..0?1 ?
1 c3?2..0?2 ? Rrc0 c3?2..0?3 ?
Rrc?0 c3?2..0?4 ? Rrc?31?0 c3?2..0?5 ?
Rrc?31?1 )

• This is equivalent to the logic expression

cond (c3?2..0?1) ??(c3?2..0?2)?(Rrc0) ?
(c3?2..0?3)??(Rrc0) ? (c3?2..0?4)??Rrc?3
1??? (c3?2..0?5)?Rrc?31?
32
Fig. 4.10 Computation of the Conditional Value
CON

• NOR gate does 0 test of Rrc on bus

33
Tbl 4.11 Control Sequence for SRC Branch
Instruction, br
br ( op 8) ? (cond ? PC ? Rrb)
Step Concrete RTN Control Sequence T0-T2 Instruct
ion fetch Instruction fetch T3. CON ?
cond(Rrc) Grc, Rout, CONin T4. CON ? PC ?
Rrb Grb, Rout, CON ? PCin, End

• Condition logic is always connected to CON, so
  Rrc only needs to be put on bus in T3
• Only PCin is conditional in T4 since gating Rrb
  to bus makes no difference if it is not used

34
Summary of the Design Process

• Informal description ? formal RTN description ?
  block diagram arch. ? concrete RTN steps ?
  hardware design of blocks?? control sequences ?
  control unit and timing
• At each level, more decisions must be made
• These decisions refine the design
• Also place requirements on hardware still to be
  designed
• The nice one way process above has circularity
• Decisions at later stages cause changes in
  earlier ones
• Happens less in a text than in reality because
• Can be fixed on re-reading
• Confusing to first time student

35
Fig. 4.11 Clocking the Data Path Register
Transfer Timing

• tR2valid is the period from begin of gate signal
  till inputs to R2 are valid
• tcomb is delay through combinational logic, such
  as ALU or cond logic

36
Signal Timing on the Data Path

• Several delays occur in getting data from R1 to
  R2
• Gate delay through the 3-state bus drivertg
• Worst case propagation delay on bustbp
• Delay through any logic, such as ALUtcomb
• Set up time for data to affect state of R2tsu
• Data can be strobed into R2 after this time
• tR2valid tg tbp tcomb tsu
• Diagram shows strobe signal in the form for a
  latch. It must be high for a minimum timetw
• There is a hold time, th, for data after strobe
  ends

37
Effect of Signal Timing on Minimum Clock Cycle

• A total latch propagation delay is the sum
• Tl tsu tw th
• All above times are specified for latch
• th may be very small or zero
• The minimum clock period is determined by finding
  longest path from ff output to ff input
• This is usually a path through the ALU
• Conditional signals add a little gate delay
• Using this path, the minimum clock period is
• tmin tg tbp tcomb tl

38
Latches Versus Edge Triggered or Master Slave
Flip-Flops

• During the high part of a strobe a latch changes
  its output
• If this output can affect its input, an error can
  occur
• This can influence even the kind of concrete RTs
  that can be written for a data path
• If the C register is implemented with latches,
  then C ? C MD is not legal
• If the C register is implemented with
  master-slave or edge triggered flip-flops, it is
  OK

39
The Control Unit

• The control units job is to generate the control
  signals in the proper sequence
• Things the control signals depend on
• The time step Ti
• The instruction op code (for steps other than T0,
  T1, T2)
• Some few data path signals like CON, n0, etc.
• Some external signals reset, interrupt, etc. (to
  be covered)
• The components of the control unit are a time
  state generator, instruction decoder, and
  combinational logic to generate control signals

40
Fig. 4.12 Control Unit Detail with Inputs and
Outputs
.
41
Synthesizing Control Signal Encoder Logic

• Design process
• Comb through the entire set of control
  sequences.
• Find all occurrences of each control signal.
• Write an equation describing that signal.
• Example Gra T5(add addi) T6st T7shr
  ...

42
Use of Data Path Conditions in Control Signal
Logic

• Example Grc T4add T4(n0)shr ...

43
Fig. 4.13 Generation of the logic for Cout and
Gra
44
Fig. 4.14 Branching in the Control Unit
.

• 3-state gates allow 6 to be applied to counter
  input
• Reset will synchronously reset counter to step T0

45
Fig. 4.15 Clocking Logic Start, Stop, and
Memory Synchronization

• Mck is master clock oscillator

46
Have Completed One-Bus Design of SRC

• High level architecture block diagram
• Concrete RTN steps
• Hardware design of registers and data path logic
• Revision of concrete RTN steps where needed
• Control sequences
• Register clocking decisions
• Logic equations for control signals
• Time step generator design
• Clock run, stop, and synchronization logic

47
Other Architectural designs will require a
different RTN

• More data paths allow more things to be done in
  one step
• Consider a two bus design
• By separating input and output of ALU on
  different buses, the C register is eliminated
• Steps can be saved by strobing ALU results
  directly into their destinations

48
Fig. 4.16 The 2-bus Microarchitecture

• Bus A carries data going into registers
• Bus B carries data being gated out of registers
• ALU function CB is used for all simple register
  transfers

49
Tbl 4.13 Concrete RTN and Control Sequence for
2-bus SRC add
Step Concrete RTN Control Sequence T0. MA ?
PC PCout, CB, MAin, Read T1. PC ? PC 4 MD
? MMA PCout, Inc4, PCin, Wait T2. IR ?
MD MDout, CB, IRin T3. A ? Rrb Grb,
Rout, CB, Ain T4. Rra ? A Rrc Grc,
Rout, ADD, Sra, Rin, End

• Note the appearance of Grc to gate the output of
  the register rc onto the B bus and Sra to select
  ra to receive data strobed from the A bus
• Two register select decoders will be needed
• Transparent latches will be required for MA at
  step T0

50
Performance and Design
51
Speedup Due To Going to 2 Buses

• Assume for now that IC and t dont change in
  going from 1 bus to 2 buses
• Naively assume that CPI goes from 8 to 7 clocks.

Class Problem How will this speedup change if
clock period of 2-bus machine is increased by 10?
52
3-bus Architecture Shortens Sequences Even More

• A 3-bus architecture allows both operand inputs
  and the output of the ALU to be connected to
  buses
• Both the C output register and the A input
  register are eliminated
• Careful connection of register inputs and outputs
  can allow multiple RTs in a step

53
Fig. 4.17 The 3-Bus SRC Design

• A-bus is ALU operand 1, B-bus is ALU operand 2,
  and C-bus is ALU output
• Note MA input connected to the B-bus

54
Tbl 4.15 SRC add Instruction for the3-bus
Microarchitecture
Step Concrete RTN Control Sequence T0. MA ? PC
PC ? PC 4 PCout, MAin, Inc4, PCin, MD ?
MMA Read, Wait T1. IR ? MD MDout,
CB, IRin T2. Rra ? Rrb Rrc GArc, RAout,
GBrb, RBout, ADD, Sra, Rin, End

• Note the use of 3 register selection signals in
  step T2 GArc, GBrb, and Sra
• In step T0, PC moves to MA over bus B and goes
  through the ALU Inc4 operation to reach PC again
  by way of bus C
• PC must be edge triggered or master-slave
• Once more MA must be a transparent latch

55
Performance and Design

• How does going to three buses affect performance?
• Assume average CPI goes from 8 to 4, while ?
  increases by 10

56
Processor Reset Function

• Reset sets program counter to a fixed value
• May be a hardwired value, or
• contents of a memory cell whose address is
  hardwired
• The control step counter is reset
• Pending exceptions are prevented, so
  initialization code is not interrupted
• It may set condition codes (if any) to known
  state
• It may clear some processor state registers
• A soft reset makes minimal changes PC, T
  (T-step counter)
• A hard reset initializes more processor state

57
SRC Reset Capability

• We specify both a hard and soft reset for SRC
• The Strt signal will do a hard reset
• It is effective only when machine is stopped
• It resets the PC to zero
• It resets all 32 general registers to zero
• The Soft Reset signal is effective when the
  machine is running
• It sets PC to zero
• It restarts instruction fetch
• It clears the Reset signal
• Actions are described in instruction_interpretatio
  n

58
Abstract RTN for SRC Reset and Start
Processor State Strt Start signal Rst Extern
al reset signal instruction_interpretation
( ?Run?Strt ? (Run ??1 PC, R0..31 ?
0) Run??Rst ? (IR ??MPC PC ??PC
4 instruction_execution) Run?Rst ? ( Rst ??0
PC ? 0) instruction_interpretation)
59
Resetting in the Middle of Instruction Execution

• The abstract RTN implies that reset takes effect
  after the current instruction is done
• To describe reset during an instruction, we must
  go from abstract to concrete RTN

• Questions for discussion
• Why might we want to reset in the middle of an
  instruction?
• How would we reset in the middle of an
  instruction?

60
Tbl 4.17 Concrete RTN Describing Reset During
add Instruction Execution
Step Concrete RTN T0 ?Reset ??(MA ??PC C ??PC
4) Reset ??(Reset ??0 PC ??0 T
?0) T1 ?Reset ??(MD ??MMA P ??C) Reset
??(Reset ??0 PC ??0 T ??0) T2 ?Reset ??(IR
??MD) Reset ??(Reset ??0 PC ??0 T
??0) T3 ?Reset ??(A ??Rrb) Reset ??(Reset
??0 PC ??0 T ??0) T4 ?Reset ??(C ??A
Rrc) Reset ??(Reset ??0 PC ??0 T
??0) T5 ?Reset ???(Rra ??C) Reset
??(Reset ??0 PC ??0 T ??0)
61
Control Sequences Including the Reset Function
Step Control Sequence T0. ?Reset ? (PCout, MAin,
Inc4, Cin, Read) Reset ? (ClrPC, ClrR,
Goto0) T1 ?Reset ? (Cout, PCin, Wait) Reset
? (ClrPC, ClrR, Goto0)  

• ClrPC clears the program counter to all zeros,
  and ClrR clears the one bit Reset flip-flop
• Because the same reset actions are in every step
  of every instruction, their control signals are
  independent of time step or op code

62
General Comments on Exceptions

• An exception is an event that causes a change in
  the program specified flow of control
• Because normal program execution is interrupted,
  they are often called interrupts
• We will use exception for the general term and
  use interrupt for an exception caused by an
  external event, such as an I/O device condition
• The usage is not standard. Other books use these
  words with other distinctions, or none

63
Combined Hardware/Software Response to an
Exception

• The system must control the type of exceptions it
  will process at any given time
• The state of the running program is saved when an
  allowed exception occurs
• Control is transferred to the correct software
  routine, or handler for this exception
• This exception, and others of less or equal
  importance are disallowed during the handler
• The state of the interrupted program is restored
  at the end of execution of the handler

64
Hardware Required to Support Exceptions

• To determine relative importance, a priority
  number is associated with every exception
• Hardware must save and change the PC, since
  without it no program execution is possible
• Hardware must disable the current exception lest
  is interrupt the handler before it can start
• Address of the handler is called the exception
  vector and is a hardware function of the
  exception type
• Exceptions must access a save area for PC and
  other hardware saved items
• Choices are special registers or a hardware stack

65
New Instructions Needed to Support Exceptions

• An instruction executed at the end of the handler
  must reverse the state changes done by hardware
  when the exception occurred
• There must be instructions to control what
  exceptions are allowed
• The simplest of these enable or disable all
  exceptions
• If processor state is stored in special registers
  on an exception, instructions are needed to save
  and restore these registers

66
Kinds of Exceptions

• System reset
• Exceptions associated with memory access
• Machine check exceptions
• Data access exceptions
• Instruction access exceptions
• Alignment exceptions
• Program exceptions
• Miscellaneous hardware exceptions
• Trace and debugging exceptions
• Non-maskable exceptions
• External exceptionsinterrupts

67
An Interrupt Facility for SRC

• The exception mechanism for SRC handles external
  interrupts
• There are no priorities, but only a simple enable
  and disable mechanism
• The PC and information about the source of the
  interrupt are stored in special registers
• Any other state saving is done by software
• The interrupt source supplies 8 bits that are
  used to generate the interrupt vector
• It also supplies a 16 bit code carrying
  information about the cause of the interrupt

68
SRC Processor State Associated with Interrupts
Processor interrupt mechanism ireq interrupt
request signal iack interrupt acknowledge
signal IE one bit interrupt enable
flag IPC?31..0? storage for PC saved upon
interrupt II?15..0? info. on source of last
interrupt Isrc_info?15..0? information from
interrupt source Isrc_vect?7..0? type code
from interrupt source Ivect?31..0?
20_at_0Isrc_vect?7..0?4_at_0
From Dev.? To Dev. ? Internal ? to CPU
? ? From Dev.? From Dev
? Internal ?
Ivect?31..0?
0000
Isrc_vect?7..0?
000 . . . 0
31
0
3
4
11
12
69
SRC Instruction Interpretation Modified for
Interrupts
instruction_interpretation (?Run?Strt ? Run ?
1 Run??(ireq?IE) ? (IR?? MPC PC ? PC 4
instruction_execution) Run?(ireq?IE) ? (IPC ?
PC?31..0? II?15..0? ??Isrc_info?15..0? iack
??1 IE ??0 PC ? Ivect?31..0? iack ? 0)
instruction_interpretation)

• If interrupts are enabled, PC and interrupt info.
  are stored in IPC and II, respectively
• With multiple requests, external priority circuit
  (discussed in later chapter) determines which
  vector info. are returned
• Interrupts are disabled
• The acknowledge signal is pulsed

70
SRC Instructions to Support Interrupts
Return from interrupt instruction rfi ( op 29
) ? (PC ? IPC IE ? 1) Save and restore
interrupt state svi ( op 16) ? (Rra?15..0?
? II?15..0? Rrb ? IPC?31..0?) ri ( op 17)
? (II?15..0? ? Rra?15..0? IPC?31..0?
??Rrb) Enable and disable interrupt
system een ( op 10 ) ? (IE ? 1) edi ( op
11 ) ? (IE ? 0)

• The 2 rfi actions are indivisible, cant een
  branch

71
Concrete RTN for SRC Instruction Fetch with
Interrupts

• PC could be transferred to IPC over the bus
• II and IPC probably have separate inputs for the
  externally supplied values
• Iack is pulsed, described as ?1 ?0, which is
  easier as a control signal than in RTN

72
Exceptions During Instruction Execution

• Some exceptions occur in the middle of
  instructions
• Some CISCs have very long instructions, like
  string move
• Some exception conditions prevent instruction
  completion, like uninstalled memory
• To handle this sort of exception, the CPU must
  make special provision for restarting
• Partially completed actions must be reversed so
  the instruction can be re-executed after
  exception handling
• Information about the internal CPU state must be
  saved so that the instruction can resume where it
  left off
• We will see that this problem is acute with
  pipeline designsalways in middle of instructions.

73
Recap of the Design Process the Main Topic of
Chap. 4
SRC
Chapter 2
Chapter 4
74
Chapter 4 Summary

• Chapter 4 has done a non pipelined data path, and
  a hardwired controller design for SRC
• The concepts of data path block diagrams,
  concrete RTN, control sequences, control logic
  equations, step counter control, and clocking
  have been introduced
• The effect of different data path architectures
  on the concrete RTN was briefly explored
• We have begun to make simple, quantitative
  estimates of the impact of hardware design on
  performance
• Hard and soft resets were designed
• A simple exception mechanism was supplied for SRC