CS 42906290 Lecture 04 Appendices

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CS 4290/6290 Lecture 04Appendices

• (Lectures based on the work of Jay Brockman,
  Sharon Hu, Randy Katz, Peter Kogge, Bill Leahy,
  Ken MacKenzie, Richard Murphy, Michael Niemier,
  and Milos Pruvlovic)

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Appendix A

• MIPS Dataflow Development

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Instruction Fetch Unit

• Fetch the instruction memPC ,
• Update the program counter
• sequential code PC lt- PC4
• branch and jump PC lt- something else

PC
Next Addr Logic
Address
Instruction Word 32
Instruction Memory
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R-Type Instructions

• Instruction format
• RTL
• Instruction fetch memPC
• ALU operation regrd lt- regrs op regrt
• Go to next instruction Pc lt- PC 4
• Ra, Rb and Rw are from instructions rs, rt, rd
  fields.
• Actual ALU operation and register write should
  occur after decoding the instruction.

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Datapath for R-Type Instructions
ALUctr
RegWr
5
Ra
32 32-bit Registers
rs
BusA 32
5
Rb
rt
ALU
5
Rw
rd
BusB 32
BusW 32

• Register timing
• Register can always be read.
• Register write only happens when RegWr is set to
  high and at the falling edge of the clock

(note, unlike LC2200, multiple read ports here)
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I-Type Arithmetic/Logic Instructions

• Instruction format
• RTL for arithmetic operations e.g., ADDI
• Instruction fetch memPC
• Add operation regrt lt- regrs
  SignExt(imm16)
• Go to next instruction Pc lt- PC 4
• Also, immediate instructions

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Datapath for I-Type A/L Instructions
note that we reuse ALU
ALUctr
RegWr
5
Ra
32 32-bit Registers
rs
BusA 32
5
Rb
rt
ALU
Rw
BusB 32
5
32
BusW 32
RegDst
Extender
ALUSrc
16
must zero out 1st 16 bits
rd
rt
imm16
In MIPS, destination registers are in
different places in opcode ? therefore we need a
mux
BusW 32
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I-Type Load/Store Instructions

• Instruction format
• RTL for load/store operations e.g., LW
• Instruction fetch memPC
• Compute memory address Addr lt- regrs
  SignExt(imm16)
• Load data into register regrt lt- memAddr
• Go to next instruction Pc lt- PC 4
• How about store?

same thing, just skip 3rd step (memaddr ?
regrs)
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Datapath for Load/Store Instructions
need a control signal
address input
32 bits of data
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I-Type Branch Instructions

• Instruction format
• RTL for branch operations e.g., BEQ
• Instruction fetch memPC
• Compute conditon Cond lt- regrs - regrt
• Calculate the next instructions address
• if (Cond eq 0) then
• PC lt- PC 4 (SignExd(imm16) x 4)
• else ?

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Datapath for Branch Instructions
PC
Next Addr Logic
To Instruction Mem
RegWr
ALUctr
5
Ra
32 32-bit Registers
rs
BusA 32
5
Rb
rt
ALU
Rw
BusB 32
5
MUX
well define this next (will need PC, zero
test condition from ALU)
32
Zero
MUX
ALUSrc
RegDst
Extender
16
rt
rd
imm16
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Next Address Logic
Detail I dont Expect you to know Here for
completeness
contains PC 4
(why 30? subtlety see Chapter 5 in your text)
1
PC
CarryIn
30
ADD
Instruction Memory
30
May not want to change PC if BEQ condition not
met (implicitly says this stuff happens anyway
so we have to be sure we dont change things
we dont want to change)
0
MUX
30
SignExt
if branch instruction AND 0, can
automatically generate control signal
16
Zero
Branch
imm16
When does the correct new PC become available?
Can we do better?
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J-Type Jump Instructions

• Instruction format
• RTL operations e.g., BEQ
• Instruction fetch memPC
• Set up PC PC lt- ((PC 4)lt3129gt
  CONCAT(targetlt250gt) x 4

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Instruction Fetch Unit
Use New address in jump instruction OR use 4
MSB of PC
(why PClt3128gt subtlety see Page 383 in your
text)
PClt3128gt
Instructionlt250gt
1
PC
CarryIn
Jump
30
ADD
30
0
30
Instruction Memory
SignExt
16
Detail I dont Expect you to know Here for
completeness
Branch
Zero
imm16
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A Single Cycle Datapath
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Appendix B

• MIPS Pipeline Example

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Executing Instructions in Pipelined Datapath

• Following charts describe 3 scenarios
• Processing of load word (lw) instruction
• Bug included in design (make SURE you understand
  the bug)
• Processing of lw
• Bug corrected (make SURE you understand the fix)
• Processing of lw followed in pipeline by sub
• (Sets the stage for discussion of HAZARDS and
  inter-instruction dependencies)

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Load word Cycle 1
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Load Word Cycle 2
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Load Word Cycle 3
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Load Word Cycle 4
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Load Word Cycle 5
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Load Word Fixed Bug
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A 2 instruction sequence

• Examine multiple-cycle single-cycle diagrams
  for a sequence of 2 independent instructions
• (i.e. no common registers b/t them)
• lw 10, 9(1)
• sub 11, 2, 3

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Single-cycle diagrams cycle 1
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Single-cycle diagrams cycle 2
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Single-cycle diagrams cycle 3
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Single-cycle diagrams cycle 4
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Single-cycle diagrams cycle 5
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Single-cycle diagrams cycle 6