Introduction to Field Programmable Gate Arrays FPGAs

1
Introduction toField Programmable Gate Arrays
FPGAs

• John Coughlan
• Technology Department

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Outline

• Q. What does FPGA stand for?
• FPGA Architecture
• Common characteristics
• Specialised blocks
• FPGA Design Flow
• Hardware Description Languages
• Design Tools
• FPGAs Applications
• Particle Physics
• Computing
• Trends and Future of FPGAs

3
What does FPGA stand for?

• Field Programmable Gate Array
• Field in the field
• Programmable Re-Configurable Change Logic
  Functions
• Gate Array reference to ASIC internal
  architecture

4
What is an FPGA?

• Field Programmable Gate Array
• (Very) Large Scale Integrated Circuit
• Digital Logic
• Programmed after manufacture rather than
  unchangeable Application Specific Integrated
  Circuit ASIC
• First appeared in 1980s. Took off in last
  decade.
• Standard IC manufacturing process
• Following Moores Law

5
Why are they of Interest?

• Essential Components in modern HEP Electronics (
  Industry!)
• Data Acquisition (Millions Channels)
• Triggers
• Computer Interfaces VME

6
What is an FPGA?

• Field Programmable Gate Array
• Configurable (Programmable) General Logic Blocks
• Configurable Interconnects
• Plus Special Purpose Blocks (Embedded Processors)
• Configured (multiple times) to perform variety of
  tasks (HEP)
• Simple Logic Block Islands in a Sea of
  Interconnects
• 10,000 100,000 (Massively Parallel HEP)

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Little bit of History

• FPGAs appeared in the 1980s. Took off in last
  decade.
• Bridge gap between simple Programmable Logic and
  semi custom ASICs (Application Specific
  Integration Circuits).

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Previous Generations Logic Devices

• Simple Logic (used to glue other ICs together)
• Reprogrammable (UV light, electrically eraseable)
• Cheap
• Easy to Program
• Many different variations
• Eg. Implement Logic as Sum of Products Terms

9
Little bit of History
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ASICs

• Large Complex Functions
• Customised for Extremes of Speed, Low Power,
  Radiation Hard (HEP)
• (Very) Expensive (in small quantities) _at_ 90 nm
  1M mask set
• (Very) Hard to Design.
• Long Design cycles.
• Not Reprogrammable. High Risk
• Semi Custom Gate Arrays.

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FPGAs best of both worlds

• Large Complex Functions
• Programmability, Flexibility.
• Massively Parallel Architecture
• Fast Turnaround Designs
• Mass produced. Cheap
• Prototype ASICs
• Power Hungry

12
Common FPGA Characteristics

• Logic Elements
• Lookup Table
• Flip Flops
• Multiplexers
• Memory Resources
• SRAM blocks
• Routing Resources
• Hierarchy Programmable Channels between Logic
  Elements
• Configurable I/O
• Interfaces to the real world. Logic Levels. Fast
  Serial I/O
• Massively Parallel Architecture (HEP)
• Clocked Logic Design
• CMOS based using SRAM cells for configuration

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Logic Elements

• Lookup Table LUTs (Combinatorial Logic)
• Multiplexers
• Flip-Flops (Clocked Registered Logic)
• Options configured by SRAM cells

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Memory

• SRAM blocks
• Data Buffers (HEP)
• FIFOs
• Code

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System on a Chip

• Recently Embedded Micro-Processors in Fabric
• Hard Cores e.g. RISC PowerPC
• Soft Cores
• Peripherals Timers, GPIO
• Run Operating System e.g. Linux
• Combine Micro-Processor
• Massively Parallel Logic
• Dual Design Flows
• Firmware HDL
• Software C

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Input and Output

• Several hundred of I/O pins
• All flavours of Logic Levels e.g. LVDS, TTL
• High Speed Serial Transceivers (up to 10? Gbps)
  (HEP)
• Ethernet MAC Cores

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Ethernet FPGA and PC Networks

• Ethernet MAC COREs inside FPGA
• Drive Data via Serialiser I/O and Optical
  Transceiver chip
• Direct to Network Card in PC.
• 2 IP Nodes on Network.
• Small DAQ systems

Dev Board
V2 Pro FPGA Rocket IO MGTs
Prog Data Generator
Gigabit Ethernet
RAID 0
SFP Gb Opto Transceiver
Quixtream UDP core
Tx1
PC
Tx2
Tx3
Gb NIC
Tx4
Prog Data Generator
Rx1
Trigger
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Programming an FPGA

• Field Programmable Gate Array
• Configurable (Programmable) General Logic Blocks
• Configurable Interconnects
• Bit File contains the Configuration Information

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Programming (Configuring) an FPGA

• SRAM cells holding configuration are Volatile
  Memory
• Lose configuration when board power is turned
  off.
• Keep Bit Pattern describes the Logic Functions in
  non-Volatile Memory e.g. ROM or Compact Flash
  card
• Reprogramming takes secs
• Uses JTAG Boundary Scan

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Design Flows

• High level Description of Logic Design
• Schematic
• Hardware Description Language
• Compile into Netlist. Low (Logic Gates) level
  description.
• Target Netlist to FPGA Fabric
• Mapping and Packing
• Placing and Routing
• Tools Generate the Bit File
• Simulation
• Timing Analysis

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Design Flows

• Schematic Capture of Logic Design.
• Useful at Top level.
• Create Netlist. Text file with signal
  connections.

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Hardware Description Languages

• Behavioural / Register Transfer Level Description
• Program Statements. Loops. If Statements etc
• Describing Mixture of Combinatorial and
  Sequential Logic and Signals between.
• Engineers call it Firmware
• VHDL (VHSIC Hardware Description Language)
• Very High Speed Integrated Circuit
• VERILOG (US)
• Synthesis (Compilation)
• Generate Netlist

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VHDL Firmware Hardware Description
architecture Behavioral of dpmbufctrl is
signal acount std_logic_vector(31 downto
0) signal dcount std_logic_vector(31
downto 0) signal bram_addr_i
std_logic_vector(31 downto 0)
begin bram_en lt'1' bram_rst lt '0' --bit
order reverse address and data buses to match EDK
scheme bram_addr(0 to 31) lt bram_addr_i(31
downto 0) --N.B. EDK DOCM addresses are byte
orientated count in 4s for whole words g1
process(clk, rst) variable state
integer range 0 to 3 variable buf_zone
integer range 0 to 1 begin if clk'event
and clk '1' then if rst '1' then
buf_zone0 acount lt (others gt '0')
dcount lt (others gt '0') bram_wen lt
(others gt '0') bram_addr_i lt X"00001FFC"
-- bram_dout_i lt (others gt '0')
state0 elsif state 0 then --wait for
din(0) at address 1FFC to be set to zero
--what about pipeline of BRAM - need to wait
before polling? bram_wen lt (others gt
'0') acount lt (others gt '0')
bram_addr_i lt X"00001FFC" bram_dout_i lt
(others gt '0') dcount lt dcount if
bram_din_i X"00000000" then state 1
else state 0 end if
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Hardware Description Languages

• View Logic as collection of Processes operating
  in Parallel
• Language Constructs for Multiplexers, FlipFlops
  etc
• Restrictive set of RTL for Synthesis
• Synthesis Tools recognise certain code constructs
  and generate appropriate logic

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FPGA Design Synchronous Logic

• Pipelined. Clocked Logic.
• Combinational and Sequential Logic.
• Register Transfer Level Logic.

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VHDL Firmware is Not a Computer Program
/ C/C / a 6 / C/C init / b 2 /
C/C init / a b b a / a 2 and b 2
sequential /
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VHDL Firmware is Not a Computer Program
/ C/C / a 6 / C/C init / b 2 /
C/C init / a b b a / a 2 and b 2
sequential /

• But

/ HDL / a 6 / HDL register init / b 2 /
HDL register init / a b b a / a 2
but b 6 concurrent /
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Hardware Description Languages

• Synthesis (Compilation)
• Generate Netlist

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Software Languages?

• Can Logic be expressed at a higher level of
  Abstraction?
• Familiar to Software Programmer?
• System C
• C/C Representation of Algorithms
• Class based
• Faster simulation
• Auto translation to HDL
• Lacks support by Tools
• Augmented C
• Special Statements to support
• Concurrency, clocks, pins ..etc
• Digital Signal Processing Functions

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Firmware Libraries

• Libraries of Firmware aka IP (Intellectual
  Property), Cores
• Buy from FPGA Vendor
• Buy from Third Parties
• Open Source
• Libraries
• VHDL code
• Black Box NetList
• Hardwired in Silicon
• Large User Community

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Debugging Designs

• Logic Simulation Tools
• Create Computer model of Logic
• Feed Test Vector signals in and compare output
  with expected pattern
• Virtual Logic Analysers
• Capture signals in real time whilst FPGA is
  running logic

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15 Years Evolution

• SRAM based FPGA devices following Moores Law
• 200 x Logic
• 40 x Faster
• Logic Element cost 1 in 1990 0.002 in 2004

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Trends

• State of Art is 65nm on 300 mm wafers
• Top of range 100,000 Logic Elements
• 1,000 pins (Ball Grid Arrays)
• Same cost
• 1995 500 Logic Elements
• 2000 10,000 Logic Elements
• 2005 50,000 Logic Elements
• Challenges
• Power. Leakage currents.
• Signal Integrity
• Design complexity

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FPGA Manufactures Market Share
2.3B
2.6B
4.1B
2.6B
2.1B
2.6B
3.1B
100
32
33
31
32
32
31
34
80
60
Market Share ()
40
51
50
49
44
38
35
20
30
0
Calendar year 1998
1999
2000
2001
2002
2003
2004
Xilinx
Altera
All Others
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Radiation Hardness

• FPGAs in Standard CMOS Process
• Not Designed for Very Rad Hard environments
• Not used in Front End Electronics (inside
  Detectors)
• Single Event Upsets
• SRAM Reconfigure
• Design Logic Triple Redundancy
• Are used in low level Rad environments (outside
  Detectors)
• In satellites
• On Mars

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FPGA Research Developments

• High Performance Computing
• CRAY XD1 OPTERON FPGA

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FPGA Research Developments

• Reconfigurable Computing
• Virtual Hardware

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Summary

• Q. What does FPGA stand for?

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Summary

• Overview of Field Programmable Gate Arrays
• Architecture
• Programming
• Design Flows
• Trends
• Why they are of interest (in HEP)
• Thanks for your attention
• Please come along and visit our electronics lab

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Spare Slides
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Choosing an FPGA

• Vendor
• Resources Logic
• Memory
• I/O pins
• Packaging
• Device Families
• Vendor Tools, IP Cores
• Special Purpose blocks e.g. CPUs
• Speed Grade
• Cost

42
FPGA Packaging

• FPGA Package is a little PCB
• Ball Grid Arrays
• Assembly is a critical Manufacturing Step
• Signal Integrity Issues

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Special Purpose Blocks

• Digital Signal Processing Functions
• FIR Filters
• Digital Radio
• Advantage over DSP chips Massively Parallel
  System