DepthOptimal Incremental Mapping for Field Programmable Gate Arrays

1
Depth-Optimal Incremental Mapping for Field
Programmable Gate Arrays

• Hui Huang
• Stanford University

Jason Cong Univ. of California, Los Angeles
This work was done when Mr. Huang was with
UCLA Supported by Actel, Lucent, Quickturn and
Xilinx under California MICRO Program
2
Introduction

• System design is an incremental and iterative
  process
• Systems are becoming larger
• Runtime reconfiguration system
• need fast compilation technique
• go incremental!

This work is a part of an overall effort at UCLA
in developing a highly efficient incremental
compilation system for FPGAs
3
Incremental Design Flow
4
Incremental Mapping

• Given
• Original netlist and its mapping solution
• Incremental changes
• Add/delete a gate
• Add/delete an edge
• Change the functionality of a node
• The combination of the above
• Output
• New mapping solution

5
Objectives of Incremental Mapping

• Preservability
• Preserve as much information as possible
• Efficiency
• Perform as fast as possible
• Quality
• Maintain depth optimality

6
Review of FlowMap Algorithm Cong Ding ICCAD
92
Depth optimal mapping algorithm in quadratic
runtime node label min mapping depth of the node
7
Review of FlowMap Algorithm Cong Ding ICCAD
92

• Depth optimal mapping algorithm in quadratic
  runtime
• node label min mapping depth of the node
• Labeling the network
• compute label(v) in topological order from PIs
• flow based cut computation
• Mapping solution generation
• Inefficient for incremental mapping

8
Overview of Our Incremental Mapping Algorithm

• Incremental Label Updating
• Topological order, from PI to PO
• Identify nodes whose labels will not change
• Re-label others
• Incremental Mapping Solution Generation
• Need to generate new LUTs for re-labeled nodes

9
Incremental Label Update

• Naïve approach
• Re-label all nodes on the transitive fan-out graph

10
Incremental Label Update

• Refined Approach
• If no edges were removed
• no need to re-label ns fan-outs if
• label(n) unchanged, and
• n was not inside any LUT

11
Early Stopping of Re-labeling
If we re-label u, then we need to re-label v
x
w
v
If label(w) not change, do we need to re-label x?
u
- No
12
Incremental Mapping Solution Generation

• Mark POs as visible.
• Mark re-labeled nodes as need re-map
• From PO to PI do
• If v is visible and needs re-map
• generate LUT(v)
• foreach node u ? input(LUT(v))
• mark u as visible
• mark u as need re-map if u?old mapping solution

13
Example
need re-map
x
visible
both visible and need re-map
w
other
y
v
u
14
Experiment Result
Average Speedup (FlowMap1.0)
18.7
15.2
6.4
15
Experiment Result (Contd)

• Percentage of Modified LUT/Edge
• 3.5 LUTs, 2.3 edges

16
Conclusion and Future Work

• Fast (Efficiency)
• Only affects small area (Preservability)
• Depth Optimal (Quality)

• Incremental Place Route
• Support for non-unit delay models

17
Thank You!
http//cadlab.cs.ucla.edu
18
Experiment ResultSummary

• Average Speedup
• Without edge removals 23.1x
• With edge removals 8.82x
• Overall 14x
• Percentage of Modified LUT/Edge
• Without edge removals 2.5 LUTs, 1.6 edges
• With edge removals 3.5 LUTs, 2.3 edges

19
Experiment Result
Average Speedup (FlowMap1.0)
161
111
18.7
15.2
9.6
6.4
20
Experiment Result (Contd)

• Percentage of Modified LUT/Edge
• Without edge removals 2.5 LUTs, 1.6 edges
• With edge removals 3.5 LUTs, 2.3 edges