TCU STATUS - PowerPoint PPT Presentation

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TCU STATUS

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Spartan II. 3. 3. 3. Adele DI CICCO Napoli, 27 Novembre 2003. FIFO. A. FIFO. B ... VME INTERFACE Xilinx Spartan XC2S100. INPUT STAGE Xilinx Spartan XC2S100 ... – PowerPoint PPT presentation

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Title: TCU STATUS


1
TCU STATUS
  • A.Di Cicco, M.Della Pietra, G.Fiorillo,P.Parascand
    olo

Adele DI CICCO Napoli, 27 Novembre 2003
2
Flow Chart
AWS
PMT
LTCU - PMT
AWS - LTCU
Discriminator
Discriminator
PMT Trigger condition logic
Wire planes coincidence Logic (pixel fired)
No Trigger request
PMT local trigger request?
Global trigger request
Local trigger request
PMT-pixels coincidences logic
TCU
Pixels Majority/Pattern logic
Global drift or busy?
Local drift or busy?
Acquire only fired pixels
No trigger
Acquire all crates
TS
Adele DI CICCO Napoli, 27 Novembre 2003
3
GLOBAL/LOCAL trigger BUSY logic
  • After validation of a global trigger request TS
    gives the GLOBAL_DRIFT signal to all v789 boards
  • During a GLOBAL_DRIFT, TS doesnt accept any
    other trigger request, while, during a
    GLOBAL_BUSY (DAQ dead time for acquisition data
    download from all chambers) it accepts only a
    Local Trigger request
  • During LOCAL_DRIFT it doesnt accept any other
    trigger request in the same crate

4
TS GLOBAL/LOCAL Logic
  • Trigger classification depends on
  • Energy deposition/number of PMT fired.
  • Detector occupancy
  • 2D/3D Pattern of fired pixels
  • TS gives GLOBAL trigger when a MAJORITY
    condition is met in PMT logic
  • Otherwise the wires define trigger locality

Adele DI CICCO Napoli, 27 Novembre 2003
5
T600 pixel definition
Pixel fired
86.4 cm
28.8 cm
9.6 cm
Total Number of Pixels 80
1 pixel area 0.6 m2
Total Number of Pixels 405
1 pixel area 0.14 m2
Total Number of Pixels 3780
1 pixel area 0.015 m2
6
TCU FEATURES
  • 1 boards per chamber (depending on
    segmentation)
  • VME standard
  • Each TCU module receives as input
  • Naws signals from the 20 AWS-LTCU boards of a
    chamber
  • Naws40 if sectors are made of 32x9 wires
  • Naws120 if 32x3 wires
  • Naws360 if 32 wires
  • Npmt signals from PMT-LTCU
  • Next from external (spectro, beam, ...)
  • checks Majority, 2D/3D Pattern logic conditions
  • event is labelled according to topology
  • TCU performs coincidences between
  • The wire planes (in a 3ms time windows)
  • PMT signals
  • External requests

Adele DI CICCO Napoli, 27 Novembre 2003
7
Pixel detection(using only two coordinates)
IND2
IND2 streched
3ms
Collection
Pixel
8
Time Diagram (with PMT signal)
9
PMT
Induction II S signal
Collection S signal
LTCU T1 signal
LTCU T2 signal
DT ? 3 ms
TCU Trigger request
n-bit
TS Trigger signal
Trigger dead time
DT ? 1.5 ms
10
Time Diagram
Induction II S signal
Collection S signal
LTCU T1 signal
LTCU T2 signal
DT ? 3 ms
First level TCU Trigger request
Second level TCU Trigger request
n-bit
TS Trigger signal
DT ? 1.5 ms
11
Pattern Recognition
It is necessary to store the evolution in time of
the number of fired pixel
For a long track consecutive pixels will be fired
(in different time) according to the track
direction. In this case the event is global but
we could acquire it as many local events.
In case of Supernova burst several pixels could
be fired with a big spacing in position and in
time.
It is necessary to make consecutive pictures to
store detectors activity
12
General Idea on Partial majority
Rack 11
Rack 13
  • Window runs on the detector
  • Majority condition is checked for each window

Adele DI CICCO Napoli, 27 Novembre 2003
13
General scheme TCU
IND2120
Adele DI CICCO Napoli, 27 Novembre 2003
14
Wire Coincidences FPGA Features
  • The detector is subdivided in three (or more)
    sections
  • Each section is monitored by a different WC-FPGA
  • Each WC-FPGA
  • Makes coincidences between wires of different
    directions
  • Checks the occupancy of the section
  • Detects spots, tracks, ...

Adele DI CICCO Napoli, 27 Novembre 2003
15
PMT FPGA Features
  • receives an N bit Word which defines PMT status
  • makes concidences between PMT and wires
  • makes global trigger proposals

VME interface Features
  • is directly interfaced to VME CPU and it
    establishes communication between VME and the
    rest of the board.

Adele DI CICCO Napoli, 27 Novembre 2003
16
Total Majority
ACCUMULATOR

R
Adele DI CICCO Napoli, 27 Novembre 2003
17
Wire CoincidencesFPGApreliminary
A0_B40
SYNC BLK
AND BLK
9
AA
INA
A1_B51
A2_B62
9
MASK
9
A3_B73
ENC
A4_B84
FLASH
A5_B95
13
SYNC BLK
BB
A6_B106
MASK
A7_B117
13
13
INB
Internal Xilinx Memory
A8_B128
MJLOCAL
FLASH
ADDRESS GENERATOR
ADR40
CLK
REG_C
SUM BLK
Whole Carpet Majority
ENCA2
REG_B
MJGLOBAL
ENCA3
VTH
REG_A
ENCA
18
Blocks description
  • SYNC BLK syncronizes the data and makes a picture
    of the detector when FLASH signal occours
  • AND_BLK makes coicidences between fired wires
  • ADDRESS GENERATOR produces the address for
    Multiplexer to select the sector
  • ENC sums pixel inside the sector
  • REG_A, REG_B, REG_C store three adjacent sectors
  • SUM sums pixels from adjacent sectors

Adele DI CICCO Napoli, 27 Novembre 2003
19
Ambiguous pixels
W wrong pixel R right pixel
R
R
R
R
Nature of detector introduces ambiguity
W
R
R
R
W
W
W
R
R
R
W
W
W
W
R
R
W
R
Adele DI CICCO Napoli, 27 Novembre 2003
20
Possible solutions
Rack 11
Rack 13
  • Higher segmentation
  • In this case LTCU will produce a FAST OR from a
    smaller number of boards
  • TCU will have more input signals
  • Possibility to send trigger to single board in
    the crate
  • Use of Induction1 plane

Adele DI CICCO Napoli, 27 Novembre 2003
21
Third plane use
W
W
W
Adele DI CICCO Napoli, 27 Novembre 2003
22
2nd level trigger
  • Possibility to have a two levels trigger
  • Every time a trigger condition is met the TCU
    produces a 1 level trigger and sends the
    proposal to the Supervisor
  • The TCU records the plane pictures before and
    after the event and performs a topological
    analysis in order to define locality/globality
    and type of event. It produces a second level
    trigger.

Adele DI CICCO Napoli, 27 Novembre 2003
23
Uniboard (Parascandolo,Masone)
3
3
3
ICC MASTER
ICC SLAVE1
ICC SLAVE2
ICC SLAVE3 Spartan II
FF
FF
FF
FF
FIFO A
FIFO B
FIFO A
FIFO B
FIFO A
FIFO B
FIFO A
FIFO B
EF
FAUX Spartan II
VME (J2) Spartan II
VME (J1) Spartan II
Adele DI CICCO Napoli, 27 Novembre 2003
24
UNIBOARD
25
Conclusions
  • We are working to define algorithms to perform a
    topological analisys of event in order to define
    locality and globality of event
  • We are studing the possibility to use the third
    coordinate
  • We are evaluating the possibility to have higher
    segmentation and two trigger level.
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